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Commit 480df512 authored by Veera Vegivada's avatar Veera Vegivada
Browse files

ARM: dts: msm: Add cpufreq HW device node for direwolf 

Add cpufreq HW device node to scale 4 domain-0 & 4 domain-1 cores
on direwolf SoCs.

Change-Id: If9697bd87eff71fa0cb8a3ae7fa0a04f4a0f4629
parent 24218a4b

qcom/direwolf.dtsi

+25 −0
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ 
			enable-method = "psci";

			cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;

			next-level-cache = <&L2_0>;

			qcom,freq-domain = <&cpufreq_hw 0 4>;

			L2_0: l2-cache {

				compatible = "arm,arch-cache";

				cache-level = <2>;
@@ -47,6 +48,7 @@ 
			enable-method = "psci";

			cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;

			next-level-cache = <&L2_1>;

			qcom,freq-domain = <&cpufreq_hw 0 4>;

			L2_1: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-level = <2>;
@@ -61,6 +63,7 @@ 
			enable-method = "psci";

			cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;

			next-level-cache = <&L2_2>;

			qcom,freq-domain = <&cpufreq_hw 0 4>;

			L2_2: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-level = <2>;
@@ -75,6 +78,7 @@ 
			enable-method = "psci";

			cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;

			next-level-cache = <&L2_3>;

			qcom,freq-domain = <&cpufreq_hw 0 4>;

			L2_3: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-level = <2>;
@@ -89,6 +93,7 @@ 
			enable-method = "psci";

			cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;

			next-level-cache = <&L2_4>;

			qcom,freq-domain = <&cpufreq_hw 1 4>;

			L2_4: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-level = <2>;
@@ -103,6 +108,7 @@ 
			enable-method = "psci";

			cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;

			next-level-cache = <&L2_5>;

			qcom,freq-domain = <&cpufreq_hw 1 4>;

			L2_5: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-level = <2>;
@@ -117,6 +123,7 @@ 
			enable-method = "psci";

			cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;

			next-level-cache = <&L2_6>;

			qcom,freq-domain = <&cpufreq_hw 1 4>;

			L2_6: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-level = <2>;
@@ -131,6 +138,7 @@ 
			enable-method = "psci";

			cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;

			next-level-cache = <&L2_7>;

			qcom,freq-domain = <&cpufreq_hw 1 4>;

			L2_7: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-level = <2>;
@@ -857,6 +865,23 @@ 
		#clock-cells = <1>;

	};



	cpufreq_hw: qcom,cpufreq-hw@18591000 {

		compatible = "qcom,cpufreq-hw-epss";

		reg = <0x18591000 0x1000>, <0x18592000 0x1000>;

		reg-names = "freq-domain0", "freq-domain1";



		clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;

		clock-names = "xo", "alternate";



		qcom,lut-row-size = <4>;

		#freq-domain-cells = <2>;

	};



	qcom,cpufreq-hw-debug@18591000 {

		compatible = "qcom,cpufreq-hw-epss-debug";

		qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>;

	};



	tlmm: pinctrl@f000000 {

		compatible = "qcom,direwolf-pinctrl";

		reg = <0x0F000000 0x1000000>;