Merge branches 'arm/exynos', 'arm/renesas', 'arm/rockchip', 'arm/omap',...

* QCOM IOMMU v1 Implementation

Qualcomm "B" family devices which are not compatible with arm-smmu have

a similar looking IOMMU but without access to the global register space,

and optionally requiring additional configuration to route context irqs

to non-secure vs secure interrupt line.

** Required properties:

- compatible       : Should be one of:

                        "qcom,msm8916-iommu"

                     Followed by "qcom,msm-iommu-v1".

- clock-names      : Should be a pair of "iface" (required for IOMMUs

                     register group access) and "bus" (required for

                     the IOMMUs underlying bus access).

- clocks           : Phandles for respective clocks described by

                     clock-names.

- #address-cells   : must be 1.

- #size-cells      : must be 1.

- #iommu-cells     : Must be 1.  Index identifies the context-bank #.

- ranges           : Base address and size of the iommu context banks.

- qcom,iommu-secure-id  : secure-id.

- List of sub-nodes, one per translation context bank.  Each sub-node

  has the following required properties:

  - compatible     : Should be one of:

        - "qcom,msm-iommu-v1-ns"  : non-secure context bank

        - "qcom,msm-iommu-v1-sec" : secure context bank

  - reg            : Base address and size of context bank within the iommu

  - interrupts     : The context fault irq.

** Optional properties:

- reg              : Base address and size of the SMMU local base, should

                     be only specified if the iommu requires configuration

                     for routing of context bank irq's to secure vs non-

                     secure lines.  (Ie. if the iommu contains secure

                     context banks)

** Examples:

	apps_iommu: iommu@1e20000 {

		#address-cells = <1>;

		#size-cells = <1>;

		#iommu-cells = <1>;

		compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";

		ranges = <0 0x1e20000 0x40000>;

		reg = <0x1ef0000 0x3000>;

		clocks = <&gcc GCC_SMMU_CFG_CLK>,

			 <&gcc GCC_APSS_TCU_CLK>;

		clock-names = "iface", "bus";

		qcom,iommu-secure-id = <17>;

		// mdp_0:

		iommu-ctx@4000 {

			compatible = "qcom,msm-iommu-v1-ns";

			reg = <0x4000 0x1000>;

			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;

		};

		// venus_ns:

		iommu-ctx@5000 {

			compatible = "qcom,msm-iommu-v1-sec";

			reg = <0x5000 0x1000>;

			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;

		};

	};

	gpu_iommu: iommu@1f08000 {

		#address-cells = <1>;

		#size-cells = <1>;

		#iommu-cells = <1>;

		compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";

		ranges = <0 0x1f08000 0x10000>;

		clocks = <&gcc GCC_SMMU_CFG_CLK>,

			 <&gcc GCC_GFX_TCU_CLK>;

		clock-names = "iface", "bus";

		qcom,iommu-secure-id = <18>;

		// gfx3d_user:

		iommu-ctx@1000 {

			compatible = "qcom,msm-iommu-v1-ns";

			reg = <0x1000 0x1000>;

			interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;

		};

		// gfx3d_priv:

		iommu-ctx@2000 {

			compatible = "qcom,msm-iommu-v1-ns";

			reg = <0x2000 0x1000>;

			interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;

		};

	};

	...

	venus: video-codec@1d00000 {

		...

		iommus = <&apps_iommu 5>;

	};

	mdp: mdp@1a01000 {

		...

		iommus = <&apps_iommu 4>;

	};

	gpu@01c00000 {

		...

		iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;

	};

                    to associate with its master device.  See:

                    Documentation/devicetree/bindings/iommu/iommu.txt

Optional properties:

- rockchip,disable-mmu-reset : Don't use the mmu reset operation.

			       Some mmu instances may produce unexpected results

			       when the reset operation is used.

Example:

	vopl_mmu: iommu@ff940300 {

	    the register.

  - "smi" : It's the clock for transfer data and command.

Required property for mt2701:

- mediatek,larb-id :the hardware id of this larb.

Example:

	larb1: larb@16010000 {

		compatible = "mediatek,mt8173-smi-larb";

			 <&vdecsys CLK_VDEC_LARB_CKEN>;

		clock-names = "apb", "smi";

	};

Example for mt2701:

	larb0: larb@14010000 {

		compatible = "mediatek,mt2701-smi-larb";

		reg = <0 0x14010000 0 0x1000>;

		mediatek,smi = <&smi_common>;

		mediatek,larb-id = <0>;

		clocks = <&mmsys CLK_MM_SMI_LARB0>,

			 <&mmsys CLK_MM_SMI_LARB0>;

		clock-names = "apb", "smi";

		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;

	};

S:	Supported

F:	arch/hexagon/

QUALCOMM IOMMU

M:	Rob Clark <robdclark@gmail.com>

L:	iommu@lists.linux-foundation.org

L:	linux-arm-msm@vger.kernel.org

S:	Maintained

F:	drivers/iommu/qcom_iommu.c

QUALCOMM VENUS VIDEO ACCELERATOR DRIVER

M:	Stanimir Varbanov <stanimir.varbanov@linaro.org>

L:	linux-media@vger.kernel.org

#include <linux/pci.h>

#include <linux/mutex.h>

#include <linux/iommu.h>

#include <asm-generic/pci.h>

#include <asm/pci_clp.h>

#include <asm/pci_debug.h>

	unsigned long	iommu_pages;

	unsigned int	next_bit;

	struct iommu_device iommu_dev;  /* IOMMU core handle */

	char res_name[16];

	struct zpci_bar_struct bars[PCI_BAR_COUNT];

int clp_disable_fh(struct zpci_dev *);

int clp_get_state(u32 fid, enum zpci_state *state);

/* IOMMU Interface */

int zpci_init_iommu(struct zpci_dev *zdev);

void zpci_destroy_iommu(struct zpci_dev *zdev);

#ifdef CONFIG_PCI

/* Error handling and recovery */

void zpci_event_error(void *);