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Commit 476ffe74 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "ARM: dts: msm: Enable L3 interconnect driver for Holi"

parents cb671f43 bf7744a7

qcom/holi.dtsi

+20 −21
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 
#include <dt-bindings/clock/qcom,gcc-holi.h>

#include <dt-bindings/clock/qcom,gpucc-holi.h>

#include <dt-bindings/clock/qcom,rpmcc.h>

#include <dt-bindings/interconnect/qcom,epss-l3.h>

#include <dt-bindings/interconnect/qcom,cpucp-l3.h>

#include <dt-bindings/interconnect/qcom,holi.h>

#include <dt-bindings/interconnect/qcom,icc.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -995,13 +995,12 @@ 
			<&rpmcc RPM_SMD_BIMC_A_CLK>;

	};



	epss_l3_cpu: l3_cpu@fd91000 {

		reg = <0x0fd91000 0x4000>;

		compatible = "qcom,holi-epss-l3-cpu";

	cpucp_l3_cpu: l3_cpu@fd90000 {

		reg = <0x0fd90000 0x3000>;

		compatible = "qcom,holi-cpucp-l3-cpu";

		#interconnect-cells = <1>;

		clock-names = "xo", "alternate";

		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;

		status = "disabled";

	};



	qcom,memshare {
@@ -1173,8 +1172,8 @@ 
		reg-names = "ftbl-base";

		governor = "mem_latency";

		interconnects =

			<&epss_l3_cpu MASTER_EPSS_L3_APPS

			 &epss_l3_cpu SLAVE_EPSS_L3_CPU0>;

			<&cpucp_l3_cpu MASTER_CPUCP_L3_APPS

			 &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU0>;

	};



	cpu1_cpu_l3_lat: qcom,cpu1-cpu-l3-lat {
@@ -1183,8 +1182,8 @@ 
		reg-names = "ftbl-base";

		governor = "mem_latency";

		interconnects =

			<&epss_l3_cpu MASTER_EPSS_L3_APPS

			 &epss_l3_cpu SLAVE_EPSS_L3_CPU1>;

			<&cpucp_l3_cpu MASTER_CPUCP_L3_APPS

			 &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU1>;

	};



	cpu2_cpu_l3_lat: qcom,cpu2-cpu-l3-lat {
@@ -1193,8 +1192,8 @@ 
		reg-names = "ftbl-base";

		governor = "mem_latency";

		interconnects =

			<&epss_l3_cpu MASTER_EPSS_L3_APPS

			 &epss_l3_cpu SLAVE_EPSS_L3_CPU2>;

			<&cpucp_l3_cpu MASTER_CPUCP_L3_APPS

			 &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU2>;

	};



	cpu3_cpu_l3_lat: qcom,cpu3-cpu-l3-lat {
@@ -1203,8 +1202,8 @@ 
		reg-names = "ftbl-base";

		governor = "mem_latency";

		interconnects =

			<&epss_l3_cpu MASTER_EPSS_L3_APPS

			 &epss_l3_cpu SLAVE_EPSS_L3_CPU3>;

			<&cpucp_l3_cpu MASTER_CPUCP_L3_APPS

			 &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU3>;

	};



	cpu4_cpu_l3_lat: qcom,cpu4-cpu-l3-lat {
@@ -1213,8 +1212,8 @@ 
		reg-names = "ftbl-base";

		governor = "mem_latency";

		interconnects =

			<&epss_l3_cpu MASTER_EPSS_L3_APPS

			 &epss_l3_cpu SLAVE_EPSS_L3_CPU4>;

			<&cpucp_l3_cpu MASTER_CPUCP_L3_APPS

			 &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU4>;

	};



	cpu5_cpu_l3_lat: qcom,cpu5-cpu-l3-lat {
@@ -1223,8 +1222,8 @@ 
		reg-names = "ftbl-base";

		governor = "mem_latency";

		interconnects =

			<&epss_l3_cpu MASTER_EPSS_L3_APPS

			 &epss_l3_cpu SLAVE_EPSS_L3_CPU5>;

			<&cpucp_l3_cpu MASTER_CPUCP_L3_APPS

			 &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU5>;

	};



	cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor {
@@ -1241,8 +1240,8 @@ 
		reg-names = "ftbl-base";

		governor = "mem_latency";

		interconnects =

			<&epss_l3_cpu MASTER_EPSS_L3_APPS

			 &epss_l3_cpu SLAVE_EPSS_L3_CPU6>;

			<&cpucp_l3_cpu MASTER_CPUCP_L3_APPS

			 &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU6>;

	};



	cpu7_cpu_l3_lat: qcom,cpu7-cpu-l3-lat {
@@ -1251,8 +1250,8 @@ 
		reg-names = "ftbl-base";

		governor = "mem_latency";

		interconnects =

			<&epss_l3_cpu MASTER_EPSS_L3_APPS

			 &epss_l3_cpu SLAVE_EPSS_L3_CPU7>;

			<&cpucp_l3_cpu MASTER_CPUCP_L3_APPS

			 &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU7>;

	};



	cpu0_cpu_ddr_lat: qcom,cpu0-cpu-ddr-lat {