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Commit 47503256 authored by Ralf Baechle's avatar Ralf Baechle
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MIPS: Hardwire detection of DSP ASE Rev 2 for systems, as required.



Most supported systems currently hardwire cpu_has_dsp to 0, so we also
can disable support for cpu_has_dsp2 resulting in a slightly smaller
kernel.

Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent ee80f7c7
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+2 −0
Original line number Diff line number Diff line
@@ -42,6 +42,8 @@
#define cpu_has_mips64r1	0
#define cpu_has_mips64r2	0

#define cpu_has_dsp		0
#define cpu_has_dsp2		0
#define cpu_has_mipsmt		0

#define cpu_has_64bits		0
+1 −0
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@
#define cpu_has_mips64r1		0
#define cpu_has_mips64r2		0
#define cpu_has_dsp			0
#define cpu_has_dsp2			0
#define cpu_has_mipsmt			0
#define cpu_has_userlocal		0
#define cpu_has_nofpuex			0
+1 −0
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@
#define cpu_has_mips64r2		0

#define cpu_has_dsp			0
#define cpu_has_dsp2			0
#define cpu_has_mipsmt			0
#define cpu_has_userlocal		0

+1 −0
Original line number Diff line number Diff line
@@ -53,6 +53,7 @@
#define cpu_has_mips64r2	1
#define cpu_has_mips_r2_exec_hazard 0
#define cpu_has_dsp		0
#define cpu_has_dsp2		0
#define cpu_has_mipsmt		0
#define cpu_has_vint		0
#define cpu_has_veic		0
+1 −0
Original line number Diff line number Diff line
@@ -45,6 +45,7 @@
#define cpu_has_ic_fills_f_dc	0
#define cpu_icache_snoops_remote_store	0
#define cpu_has_dsp		0
#define cpu_has_dsp2		0
#define cpu_has_mipsmt		0
#define cpu_has_userlocal	0

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