Commit 472acf15 authored Oct 19, 2021 by Guangbin Huang Committed by Greg Kroah-Hartman Oct 27, 2021

net: hns3: add limit ets dwrr bandwidth cannot be 0



[ Upstream commit 731797fdffa3d083db536e2fdd07ceb050bb40b1 ]

If ets dwrr bandwidth of tc is set to 0, the hardware will switch to SP
mode. In this case, this tc may occupy all the tx bandwidth if it has
huge traffic, so it violates the purpose of the user setting.

To fix this problem, limit the ets dwrr bandwidth must greater than 0.

Fixes: cacde272 ("net: hns3: Add hclge_dcb module for the support of DCB feature")
Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Sasha Levin <sashal@kernel.org>

parent b1f9380e

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c

+9 −0

Original line number	Diff line number	Diff line
		@@ -132,6 +132,15 @@ static int hclge_ets_validate(struct hclge_dev hdev, struct ieee_ets ets,
		*changed = true;
		break;
		case IEEE_8021QAZ_TSA_ETS:
		/* The hardware will switch to sp mode if bandwidth is
		* 0, so limit ets bandwidth must be greater than 0.
		*/
		if (!ets->tc_tx_bw[i]) {
		dev_err(&hdev->pdev->dev,
		"tc%u ets bw cannot be 0\n", i);
		return -EINVAL;
		}

		if (hdev->tm_info.tc_info[i].tc_sch_mode !=
		HCLGE_SCH_MODE_DWRR)
		*changed = true;