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Commit 471b5e42 authored by Chris Brandt's avatar Chris Brandt Committed by Russell King
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ARM: 8659/1: l2c: allow CA9 optimizations to be disabled 



If a PL310 is added to a system, but the sideband signals are not
connected, some Cortex A9 optimizations cannot be used. In particular,
enabling Full Line of Zeros in the CA9 without sidebands connected will
crash the system since the CA9 will expect the L2C to perform operations,
yet the L2C never gets the commands. Early BRESP also does not work
without sideband signals.

Signed-off-by: default avatarChris Brandt <chris.brandt@renesas.com>
Signed-off-by: default avatarRussell King <rmk+kernel@armlinux.org.uk>
parent c1ae3cfa

Documentation/devicetree/bindings/arm/l2c2x0.txt

+3 −0
Original line number Original line Diff line number Diff line
@@ -90,6 +90,9 @@ Optional properties: 
- arm,standby-mode: L2 standby mode enable. Value <0> (forcibly disable),

- arm,standby-mode: L2 standby mode enable. Value <0> (forcibly disable),

  <1> (forcibly enable), property absent (OS specific behavior,

  <1> (forcibly enable), property absent (OS specific behavior,

  preferably retain firmware settings)

  preferably retain firmware settings)

- arm,early-bresp-disable : Disable the CA9 optimization Early BRESP (PL310)

- arm,full-line-zero-disable : Disable the CA9 optimization Full line of zero

  write (PL310)





Example:

Example:

arch/arm/mm/cache-l2x0.c

+11 −2
Original line number Original line Diff line number Diff line
@@ -57,6 +57,9 @@ static unsigned long sync_reg_offset = L2X0_CACHE_SYNC; 




struct l2x0_regs l2x0_saved_regs;

struct l2x0_regs l2x0_saved_regs;





static bool l2x0_bresp_disable;

static bool l2x0_flz_disable;



/*

/*

 * Common code for all cache controllers.

 * Common code for all cache controllers.

 */

 */
@@ -620,7 +623,7 @@ static void __init l2c310_enable(void __iomem *base, unsigned num_lock) 
	u32 aux = l2x0_saved_regs.aux_ctrl;

	u32 aux = l2x0_saved_regs.aux_ctrl;





	if (rev >= L310_CACHE_ID_RTL_R2P0) {

	if (rev >= L310_CACHE_ID_RTL_R2P0) {

		if (cortex_a9) {

		if (cortex_a9 && !l2x0_bresp_disable) {

			aux |= L310_AUX_CTRL_EARLY_BRESP;

			aux |= L310_AUX_CTRL_EARLY_BRESP;

			pr_info("L2C-310 enabling early BRESP for Cortex-A9\n");

			pr_info("L2C-310 enabling early BRESP for Cortex-A9\n");

		} else if (aux & L310_AUX_CTRL_EARLY_BRESP) {

		} else if (aux & L310_AUX_CTRL_EARLY_BRESP) {
@@ -629,7 +632,7 @@ static void __init l2c310_enable(void __iomem *base, unsigned num_lock) 
		}

		}

	}

	}





	if (cortex_a9) {

	if (cortex_a9 && !l2x0_flz_disable) {

		u32 aux_cur = readl_relaxed(base + L2X0_AUX_CTRL);

		u32 aux_cur = readl_relaxed(base + L2X0_AUX_CTRL);

		u32 acr = get_auxcr();

		u32 acr = get_auxcr();
@@ -1200,6 +1203,12 @@ static void __init l2c310_of_parse(const struct device_node *np, 
		*aux_mask &= ~L2C_AUX_CTRL_PARITY_ENABLE;

		*aux_mask &= ~L2C_AUX_CTRL_PARITY_ENABLE;

	}

	}





	if (of_property_read_bool(np, "arm,early-bresp-disable"))

		l2x0_bresp_disable = true;



	if (of_property_read_bool(np, "arm,full-line-zero-disable"))

		l2x0_flz_disable = true;



	prefetch = l2x0_saved_regs.prefetch_ctrl;

	prefetch = l2x0_saved_regs.prefetch_ctrl;





	ret = of_property_read_u32(np, "arm,double-linefill", &val);

	ret = of_property_read_u32(np, "arm,double-linefill", &val);