Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Skip to content
Commit 46ac0e76 authored by Richard Schleich's avatar Richard Schleich Committed by Greg Kroah-Hartman
Browse files

ARM: dts: bcm2837: Add the missing L1/L2 cache information



[ Upstream commit bdf8762da268d2a34abf517c36528413906e9cd5 ]

This patch fixes the kernel warning
"cacheinfo: Unable to detect cache hierarchy for CPU 0"
for the bcm2837 on newer kernel versions.

Signed-off-by: default avatarRichard Schleich <rs@noreya.tech>
Tested-by: default avatarStefan Wahren <stefan.wahren@i2se.com>
[florian: Align and remove comments matching property values]
Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent bf27f5df
Loading
Loading
Loading
Loading
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment