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Commit 4686f486 authored by Tao,Zhang's avatar Tao,Zhang
Browse files

ARM: dts: msm: Disable SDCC TPDMs on shima 

Disable all SDCC TPDMs on shima first since there is SDCC internal
clock issue.

Change-Id: Iac18333769fa593a407b10eeed830e728d475c1a
parent 30e45aae

qcom/shima-coresight.dtsi

+3 −0
Original line number Diff line number Diff line
@@ -1210,6 +1210,7 @@ 
		reg-names = "tpdm-base";

		qcom,cmb-msr-skip;



		status = "disabled";

		coresight-name = "coresight-tpdm-sdcc-4";



		clocks = <&aopcc QDSS_CLK>;
@@ -1372,6 +1373,7 @@ 
		reg-names = "tpdm-base";

		qcom,cmb-msr-skip;



		status = "disabled";

		coresight-name = "coresight-tpdm-sdcc-1";



		clocks = <&aopcc QDSS_CLK>;
@@ -1394,6 +1396,7 @@ 
		reg-names = "tpdm-base";

		qcom,cmb-msr-skip;



		status = "disabled";

		coresight-name = "coresight-tpdm-sdcc-2";



		clocks = <&aopcc QDSS_CLK>;