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Commit 464c510f authored by Mars Cheng's avatar Mars Cheng Committed by Matthias Brugger
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arm64: dts: mediatek: add mt6797 support 



This adds basic chip support for MT6797 SoC.

Signed-off-by: default avatarMars Cheng <mars.cheng@mediatek.com>
Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent 1be88348

arch/arm64/boot/dts/mediatek/Makefile

+1 −0
Original line number Diff line number Diff line 
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb



always		:= $(dtb-y)

arch/arm64/boot/dts/mediatek/mt6797-evb.dts

0 → 100644
+36 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2017 MediaTek Inc.

 * Author: Mars.C <mars.cheng@mediatek.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



/dts-v1/;

#include "mt6797.dtsi"



/ {

	model = "MediaTek MT6797 Evaluation Board";

	compatible = "mediatek,mt6797-evb", "mediatek,mt6797";



	aliases {

		serial0 = &uart0;

	};



	memory@40000000 {

		device_type = "memory";

		reg = <0 0x40000000 0 0x1e800000>;

	};



	chosen {};

};



&uart0 {

	status = "okay";

};

arch/arm64/boot/dts/mediatek/mt6797.dtsi

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+182 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2017 MediaTek Inc.

 * Author: Mars.C <mars.cheng@mediatek.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#include <dt-bindings/interrupt-controller/irq.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>



/ {

	compatible = "mediatek,mt6797";

	interrupt-parent = <&sysirq>;

	#address-cells = <2>;

	#size-cells = <2>;



	psci {

		compatible = "arm,psci-0.2";

		method = "smc";

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			enable-method = "psci";

			reg = <0x000>;

		};



		cpu1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			enable-method = "psci";

			reg = <0x001>;

		};



		cpu2: cpu@2 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			enable-method = "psci";

			reg = <0x002>;

		};



		cpu3: cpu@3 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			enable-method = "psci";

			reg = <0x003>;

		};



		cpu4: cpu@100 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			enable-method = "psci";

			reg = <0x100>;

		};



		cpu5: cpu@101 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			enable-method = "psci";

			reg = <0x101>;

		};



		cpu6: cpu@102 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			enable-method = "psci";

			reg = <0x102>;

		};



		cpu7: cpu@103 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			enable-method = "psci";

			reg = <0x103>;

		};



		cpu8: cpu@200 {

			device_type = "cpu";

			compatible = "arm,cortex-a72";

			enable-method = "psci";

			reg = <0x200>;

		};



		cpu9: cpu@201 {

			device_type = "cpu";

			compatible = "arm,cortex-a72";

			enable-method = "psci";

			reg = <0x201>;

		};

	};



	clk26m: oscillator@0 {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <26000000>;

		clock-output-names = "clk26m";

	};



	clk32k: oscillator@1 {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <32000>;

		clock-output-names = "clk32k";

	};



	timer {

		compatible = "arm,armv8-timer";

		interrupt-parent = <&gic>;

		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;

	};



	sysirq: intpol-controller@10200620 {

		compatible = "mediatek,mt6797-sysirq",

			     "mediatek,mt6577-sysirq";

		interrupt-controller;

		#interrupt-cells = <3>;

		interrupt-parent = <&gic>;

		reg = <0 0x10220620 0 0x20>,

		      <0 0x10220690 0 0x10>;

	};



	uart0: serial@11002000 {

		compatible = "mediatek,mt6797-uart",

			     "mediatek,mt6577-uart";

		reg = <0 0x11002000 0 0x400>;

		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&clk26m>;

		status = "disabled";

	};



	uart1: serial@11003000 {

		compatible = "mediatek,mt6797-uart",

			     "mediatek,mt6577-uart";

		reg = <0 0x11003000 0 0x400>;

		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&clk26m>;

		status = "disabled";

	};



	uart2: serial@11004000 {

		compatible = "mediatek,mt6797-uart",

			     "mediatek,mt6577-uart";

		reg = <0 0x11004000 0 0x400>;

		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&clk26m>;

		status = "disabled";

	};



	uart3: serial@11005000 {

		compatible = "mediatek,mt6797-uart",

			     "mediatek,mt6577-uart";

		reg = <0 0x11005000 0 0x400>;

		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&clk26m>;

		status = "disabled";

	};



	gic: interrupt-controller@19000000 {

		compatible = "arm,gic-v3";

		#interrupt-cells = <3>;

		interrupt-parent = <&gic>;

		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-controller;

		reg = <0 0x19000000 0 0x10000>,    /* GICD */

		      <0 0x19200000 0 0x200000>,   /* GICR */

		      <0 0x10240000 0 0x2000>;     /* GICC */

	};

};