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Commit 4600b9cc authored Mar 13, 2020 by Jagadeesh Kona

bindings: clock: Add support for SHIMA clock controllers

Update the GCC, GPUCC, CAMCC, DISPCC, VIDEOCC and debug clock controller
bindings for SHIMA device.

Change-Id: Ia28c6e4595e78103326677772ca765f8d16b1560

parent 9fbf9f5f

bindings/clock/qcom,camcc.txt

+2 −1

Original line number	Diff line number	Diff line
		@@ -2,7 +2,8 @@ Qualcomm Technologies, Inc. Camera Clock & Reset Controller Binding
		-------------------------------------------------------------------

		Required properties :
		- compatible : shall contain "qcom,sdm845-camcc" or "qcom,lahaina-camcc".
		- compatible : shall contain "qcom,sdm845-camcc" or "qcom,lahaina-camcc",
		"qcom,shima-camcc".
		- reg : shall contain base register location and length.
		- reg-names: names of registers listed in the same order as in
		the reg property.

bindings/clock/qcom,debugcc.txt

+1 −1

Original line number	Diff line number	Diff line
		@@ -2,7 +2,7 @@ Qualcomm Technologies, Inc. Debug Clock Controller Binding
		----------------------------------------------------------

		Required properties :
		- compatible: Shall contain "qcom,lahaina-debugcc".
		- compatible: Shall contain "qcom,lahaina-debugcc" or "qcom,shima-debugcc".
		- qcom,gcc: phandle to the GCC device node.
		- qcom,videocc: phandle to the Video CC device node.
		- qcom,camcc: phandle to the Camera CC device node.

bindings/clock/qcom,dispcc.txt

+1 −0

Original line number	Diff line number	Diff line
		@@ -7,6 +7,7 @@ Required properties :

		"qcom,sdm845-dispcc"
		"qcom,lahaina-dispcc"
		"qcom,shima-dispcc"

		- reg : shall contain base register location and length.
		- #clock-cells : from common clock binding, shall contain 1.

bindings/clock/qcom,gcc.txt

+1 −0

Original line number	Diff line number	Diff line
		@@ -28,6 +28,7 @@ Required properties :
		"qcom,gcc-sm8150-v2"
		"qcom,gcc-sa8155"
		"qcom,gcc-sa8155-v2"
		"qcom,shima-gcc"


		- reg : shall contain base register location and length

bindings/clock/qcom,gpucc.txt

+2 −1

Original line number	Diff line number	Diff line
		@@ -3,7 +3,8 @@ Qualcomm Technologies, Inc. Graphics Clock & Reset Controller Binding

		Required properties :
		- compatible : shall contain "qcom,sdm845-gpucc" or "qcom,msm8998-gpucc",
		"qcom,lahaina-gpucc.
		"qcom,lahaina-gpucc",
		"qcom,shima-gpucc".
		- reg: shall contain base register offset and size.
		- reg-names: names of registers listed in the same order as in the reg property.
		Must contain "cc_base".