hisi_sas: add v2 register definitions

#include "hisi_sas.h"

#include "hisi_sas.h"

#define DRV_NAME "hisi_sas_v2_hw"

#define DRV_NAME "hisi_sas_v2_hw"

/* global registers need init*/

#define DLVRY_QUEUE_ENABLE		0x0

#define IOST_BASE_ADDR_LO		0x8

#define IOST_BASE_ADDR_HI		0xc

#define ITCT_BASE_ADDR_LO		0x10

#define ITCT_BASE_ADDR_HI		0x14

#define IO_BROKEN_MSG_ADDR_LO		0x18

#define IO_BROKEN_MSG_ADDR_HI		0x1c

#define PHY_CONTEXT			0x20

#define PHY_STATE			0x24

#define PHY_PORT_NUM_MA			0x28

#define PORT_STATE			0x2c

#define PORT_STATE_PHY8_PORT_NUM_OFF	16

#define PORT_STATE_PHY8_PORT_NUM_MSK	(0xf << PORT_STATE_PHY8_PORT_NUM_OFF)

#define PORT_STATE_PHY8_CONN_RATE_OFF	20

#define PORT_STATE_PHY8_CONN_RATE_MSK	(0xf << PORT_STATE_PHY8_CONN_RATE_OFF)

#define PHY_CONN_RATE			0x30

#define HGC_TRANS_TASK_CNT_LIMIT	0x38

#define AXI_AHB_CLK_CFG			0x3c

#define ITCT_CLR			0x44

#define ITCT_CLR_EN_OFF			16

#define ITCT_CLR_EN_MSK			(0x1 << ITCT_CLR_EN_OFF)

#define ITCT_DEV_OFF			0

#define ITCT_DEV_MSK			(0x7ff << ITCT_DEV_OFF)

#define AXI_USER1			0x48

#define AXI_USER2			0x4c

#define IO_SATA_BROKEN_MSG_ADDR_LO	0x58

#define IO_SATA_BROKEN_MSG_ADDR_HI	0x5c

#define SATA_INITI_D2H_STORE_ADDR_LO	0x60

#define SATA_INITI_D2H_STORE_ADDR_HI	0x64

#define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL	0x84

#define HGC_SAS_TXFAIL_RETRY_CTRL	0x88

#define HGC_GET_ITV_TIME		0x90

#define DEVICE_MSG_WORK_MODE		0x94

#define OPENA_WT_CONTI_TIME		0x9c

#define I_T_NEXUS_LOSS_TIME		0xa0

#define MAX_CON_TIME_LIMIT_TIME		0xa4

#define BUS_INACTIVE_LIMIT_TIME		0xa8

#define REJECT_TO_OPEN_LIMIT_TIME	0xac

#define CFG_AGING_TIME			0xbc

#define HGC_DFX_CFG2			0xc0

#define HGC_IOMB_PROC1_STATUS	0x104

#define CFG_1US_TIMER_TRSH		0xcc

#define HGC_INVLD_DQE_INFO		0x148

#define HGC_INVLD_DQE_INFO_FB_CH0_OFF	9

#define HGC_INVLD_DQE_INFO_FB_CH0_MSK	(0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF)

#define HGC_INVLD_DQE_INFO_FB_CH3_OFF	18

#define INT_COAL_EN			0x19c

#define OQ_INT_COAL_TIME		0x1a0

#define OQ_INT_COAL_CNT			0x1a4

#define ENT_INT_COAL_TIME		0x1a8

#define ENT_INT_COAL_CNT		0x1ac

#define OQ_INT_SRC			0x1b0

#define OQ_INT_SRC_MSK			0x1b4

#define ENT_INT_SRC1			0x1b8

#define ENT_INT_SRC1_D2H_FIS_CH0_OFF	0

#define ENT_INT_SRC1_D2H_FIS_CH0_MSK	(0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)

#define ENT_INT_SRC1_D2H_FIS_CH1_OFF	8

#define ENT_INT_SRC1_D2H_FIS_CH1_MSK	(0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)

#define ENT_INT_SRC2			0x1bc

#define ENT_INT_SRC3			0x1c0

#define ENT_INT_SRC3_ITC_INT_OFF	15

#define ENT_INT_SRC3_ITC_INT_MSK	(0x1 << ENT_INT_SRC3_ITC_INT_OFF)

#define ENT_INT_SRC_MSK1		0x1c4

#define ENT_INT_SRC_MSK2		0x1c8

#define ENT_INT_SRC_MSK3		0x1cc

#define ENT_INT_SRC_MSK3_ENT95_MSK_OFF	31

#define ENT_INT_SRC_MSK3_ENT95_MSK_MSK	(0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)

#define SAS_ECC_INTR_MSK		0x1ec

#define HGC_ERR_STAT_EN			0x238

#define DLVRY_Q_0_BASE_ADDR_LO		0x260

#define DLVRY_Q_0_BASE_ADDR_HI		0x264

#define DLVRY_Q_0_DEPTH			0x268

#define DLVRY_Q_0_WR_PTR		0x26c

#define DLVRY_Q_0_RD_PTR		0x270

#define HYPER_STREAM_ID_EN_CFG		0xc80

#define OQ0_INT_SRC_MSK			0xc90

#define COMPL_Q_0_BASE_ADDR_LO		0x4e0

#define COMPL_Q_0_BASE_ADDR_HI		0x4e4

#define COMPL_Q_0_DEPTH			0x4e8

#define COMPL_Q_0_WR_PTR		0x4ec

#define COMPL_Q_0_RD_PTR		0x4f0

/* phy registers need init */

#define PORT_BASE			(0x2000)

#define PHY_CFG				(PORT_BASE + 0x0)

#define HARD_PHY_LINKRATE		(PORT_BASE + 0x4)

#define PHY_CFG_ENA_OFF			0

#define PHY_CFG_ENA_MSK			(0x1 << PHY_CFG_ENA_OFF)

#define PHY_CFG_DC_OPT_OFF		2

#define PHY_CFG_DC_OPT_MSK		(0x1 << PHY_CFG_DC_OPT_OFF)

#define PROG_PHY_LINK_RATE		(PORT_BASE + 0x8)

#define PROG_PHY_LINK_RATE_MAX_OFF	0

#define PROG_PHY_LINK_RATE_MAX_MSK	(0xff << PROG_PHY_LINK_RATE_MAX_OFF)

#define PHY_CTRL			(PORT_BASE + 0x14)

#define PHY_CTRL_RESET_OFF		0

#define PHY_CTRL_RESET_MSK		(0x1 << PHY_CTRL_RESET_OFF)

#define SAS_PHY_CTRL			(PORT_BASE + 0x20)

#define SL_CFG				(PORT_BASE + 0x84)

#define PHY_PCN				(PORT_BASE + 0x44)

#define SL_TOUT_CFG			(PORT_BASE + 0x8c)

#define SL_CONTROL			(PORT_BASE + 0x94)

#define SL_CONTROL_NOTIFY_EN_OFF	0

#define SL_CONTROL_NOTIFY_EN_MSK	(0x1 << SL_CONTROL_NOTIFY_EN_OFF)

#define TX_ID_DWORD0			(PORT_BASE + 0x9c)

#define TX_ID_DWORD1			(PORT_BASE + 0xa0)

#define TX_ID_DWORD2			(PORT_BASE + 0xa4)

#define TX_ID_DWORD3			(PORT_BASE + 0xa8)

#define TX_ID_DWORD4			(PORT_BASE + 0xaC)

#define TX_ID_DWORD5			(PORT_BASE + 0xb0)

#define TX_ID_DWORD6			(PORT_BASE + 0xb4)

#define RX_IDAF_DWORD0			(PORT_BASE + 0xc4)

#define RX_IDAF_DWORD1			(PORT_BASE + 0xc8)

#define RX_IDAF_DWORD2			(PORT_BASE + 0xcc)

#define RX_IDAF_DWORD3			(PORT_BASE + 0xd0)

#define RX_IDAF_DWORD4			(PORT_BASE + 0xd4)

#define RX_IDAF_DWORD5			(PORT_BASE + 0xd8)

#define RX_IDAF_DWORD6			(PORT_BASE + 0xdc)

#define RXOP_CHECK_CFG_H		(PORT_BASE + 0xfc)

#define DONE_RECEIVED_TIME		(PORT_BASE + 0x11c)

#define CHL_INT0			(PORT_BASE + 0x1b4)

#define CHL_INT0_HOTPLUG_TOUT_OFF	0

#define CHL_INT0_HOTPLUG_TOUT_MSK	(0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)

#define CHL_INT0_SL_RX_BCST_ACK_OFF	1

#define CHL_INT0_SL_RX_BCST_ACK_MSK	(0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)

#define CHL_INT0_SL_PHY_ENABLE_OFF	2

#define CHL_INT0_SL_PHY_ENABLE_MSK	(0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)

#define CHL_INT0_NOT_RDY_OFF		4

#define CHL_INT0_NOT_RDY_MSK		(0x1 << CHL_INT0_NOT_RDY_OFF)

#define CHL_INT0_PHY_RDY_OFF		5

#define CHL_INT0_PHY_RDY_MSK		(0x1 << CHL_INT0_PHY_RDY_OFF)

#define CHL_INT1			(PORT_BASE + 0x1b8)

#define CHL_INT1_DMAC_TX_ECC_ERR_OFF	15

#define CHL_INT1_DMAC_TX_ECC_ERR_MSK	(0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)

#define CHL_INT1_DMAC_RX_ECC_ERR_OFF	17

#define CHL_INT1_DMAC_RX_ECC_ERR_MSK	(0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)

#define CHL_INT2			(PORT_BASE + 0x1bc)

#define CHL_INT0_MSK			(PORT_BASE + 0x1c0)

#define CHL_INT1_MSK			(PORT_BASE + 0x1c4)

#define CHL_INT2_MSK			(PORT_BASE + 0x1c8)

#define CHL_INT_COAL_EN			(PORT_BASE + 0x1d0)

#define PHY_CTRL_RDY_MSK		(PORT_BASE + 0x2b0)

#define PHYCTRL_NOT_RDY_MSK		(PORT_BASE + 0x2b4)

#define PHYCTRL_DWS_RESET_MSK		(PORT_BASE + 0x2b8)

#define PHYCTRL_PHY_ENA_MSK		(PORT_BASE + 0x2bc)

#define SL_RX_BCAST_CHK_MSK		(PORT_BASE + 0x2c0)

#define PHYCTRL_OOB_RESTART_MSK		(PORT_BASE + 0x2c4)

#define DMA_TX_STATUS			(PORT_BASE + 0x2d0)

#define DMA_TX_STATUS_BUSY_OFF		0

#define DMA_TX_STATUS_BUSY_MSK		(0x1 << DMA_TX_STATUS_BUSY_OFF)

#define DMA_RX_STATUS			(PORT_BASE + 0x2e8)

#define DMA_RX_STATUS_BUSY_OFF		0

#define DMA_RX_STATUS_BUSY_MSK		(0x1 << DMA_RX_STATUS_BUSY_OFF)

#define AXI_CFG				(0x5100)

#define AM_CFG_MAX_TRANS		(0x5010)

#define AM_CFG_SINGLE_PORT_MAX_TRANS	(0x5014)

/* HW dma structures */

/* Delivery queue header */

/* dw0 */

#define CMD_HDR_RESP_REPORT_OFF		5

#define CMD_HDR_RESP_REPORT_MSK		(0x1 << CMD_HDR_RESP_REPORT_OFF)

#define CMD_HDR_TLR_CTRL_OFF		6

#define CMD_HDR_TLR_CTRL_MSK		(0x3 << CMD_HDR_TLR_CTRL_OFF)

#define CMD_HDR_PORT_OFF		18

#define CMD_HDR_PORT_MSK		(0xf << CMD_HDR_PORT_OFF)

#define CMD_HDR_PRIORITY_OFF		27

#define CMD_HDR_PRIORITY_MSK		(0x1 << CMD_HDR_PRIORITY_OFF)

#define CMD_HDR_CMD_OFF			29

#define CMD_HDR_CMD_MSK			(0x7 << CMD_HDR_CMD_OFF)

/* dw1 */

#define CMD_HDR_DIR_OFF			5

#define CMD_HDR_DIR_MSK			(0x3 << CMD_HDR_DIR_OFF)

#define CMD_HDR_RESET_OFF		7

#define CMD_HDR_RESET_MSK		(0x1 << CMD_HDR_RESET_OFF)

#define CMD_HDR_VDTL_OFF		10

#define CMD_HDR_VDTL_MSK		(0x1 << CMD_HDR_VDTL_OFF)

#define CMD_HDR_FRAME_TYPE_OFF		11

#define CMD_HDR_FRAME_TYPE_MSK		(0x1f << CMD_HDR_FRAME_TYPE_OFF)

#define CMD_HDR_DEV_ID_OFF		16

#define CMD_HDR_DEV_ID_MSK		(0xffff << CMD_HDR_DEV_ID_OFF)

/* dw2 */

#define CMD_HDR_CFL_OFF			0

#define CMD_HDR_CFL_MSK			(0x1ff << CMD_HDR_CFL_OFF)

#define CMD_HDR_NCQ_TAG_OFF		10

#define CMD_HDR_NCQ_TAG_MSK		(0x1f << CMD_HDR_NCQ_TAG_OFF)

#define CMD_HDR_MRFL_OFF		15

#define CMD_HDR_MRFL_MSK		(0x1ff << CMD_HDR_MRFL_OFF)

#define CMD_HDR_SG_MOD_OFF		24

#define CMD_HDR_SG_MOD_MSK		(0x3 << CMD_HDR_SG_MOD_OFF)

#define CMD_HDR_FIRST_BURST_OFF		26

#define CMD_HDR_FIRST_BURST_MSK		(0x1 << CMD_HDR_SG_MOD_OFF)

/* dw3 */

#define CMD_HDR_IPTT_OFF		0

#define CMD_HDR_IPTT_MSK		(0xffff << CMD_HDR_IPTT_OFF)

/* dw6 */

#define CMD_HDR_DIF_SGL_LEN_OFF		0

#define CMD_HDR_DIF_SGL_LEN_MSK		(0xffff << CMD_HDR_DIF_SGL_LEN_OFF)

#define CMD_HDR_DATA_SGL_LEN_OFF	16

#define CMD_HDR_DATA_SGL_LEN_MSK	(0xffff << CMD_HDR_DATA_SGL_LEN_OFF)

/* Completion header */

/* dw0 */

#define CMPLT_HDR_RSPNS_XFRD_OFF	10

#define CMPLT_HDR_RSPNS_XFRD_MSK	(0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)

#define CMPLT_HDR_ERX_OFF		12

#define CMPLT_HDR_ERX_MSK		(0x1 << CMPLT_HDR_ERX_OFF)

/* dw1 */

#define CMPLT_HDR_IPTT_OFF		0

#define CMPLT_HDR_IPTT_MSK		(0xffff << CMPLT_HDR_IPTT_OFF)

#define CMPLT_HDR_DEV_ID_OFF		16

#define CMPLT_HDR_DEV_ID_MSK		(0xffff << CMPLT_HDR_DEV_ID_OFF)

/* ITCT header */

/* qw0 */

#define ITCT_HDR_DEV_TYPE_OFF		0

#define ITCT_HDR_DEV_TYPE_MSK		(0x3 << ITCT_HDR_DEV_TYPE_OFF)

#define ITCT_HDR_VALID_OFF		2

#define ITCT_HDR_VALID_MSK		(0x1 << ITCT_HDR_VALID_OFF)

#define ITCT_HDR_MCR_OFF		5

#define ITCT_HDR_MCR_MSK		(0xf << ITCT_HDR_MCR_OFF)

#define ITCT_HDR_VLN_OFF		9

#define ITCT_HDR_VLN_MSK		(0xf << ITCT_HDR_VLN_OFF)

#define ITCT_HDR_PORT_ID_OFF		28

#define ITCT_HDR_PORT_ID_MSK		(0xf << ITCT_HDR_PORT_ID_OFF)

/* qw2 */

#define ITCT_HDR_INLT_OFF		0

#define ITCT_HDR_INLT_MSK		(0xffffULL << ITCT_HDR_INLT_OFF)

#define ITCT_HDR_BITLT_OFF		16

#define ITCT_HDR_BITLT_MSK		(0xffffULL << ITCT_HDR_BITLT_OFF)

#define ITCT_HDR_MCTLT_OFF		32

#define ITCT_HDR_MCTLT_MSK		(0xffffULL << ITCT_HDR_MCTLT_OFF)

#define ITCT_HDR_RTOLT_OFF		48

#define ITCT_HDR_RTOLT_MSK		(0xffffULL << ITCT_HDR_RTOLT_OFF)

static const struct hisi_sas_hw hisi_sas_v2_hw = {

static const struct hisi_sas_hw hisi_sas_v2_hw = {

};

};