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Commit 4597905e authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'remotes/lorenzo/pci/mobiveil' 

  - Fix mobiveil inbound window CPU base address setup (Hou Zhiqiang)

* remotes/lorenzo/pci/mobiveil:
  PCI: mobiveil: Fix the CPU base address setup in inbound window
parents e4faafbf df901c85

drivers/pci/controller/pcie-mobiveil.c

+7 −3
Original line number Diff line number Diff line
@@ -88,6 +88,7 @@ 
#define  AMAP_CTRL_TYPE_MASK		3



#define PAB_EXT_PEX_AMAP_SIZEN(win)	PAB_EXT_REG_ADDR(0xbef0, win)

#define PAB_EXT_PEX_AMAP_AXI_WIN(win)	PAB_EXT_REG_ADDR(0xb4a0, win)

#define PAB_PEX_AMAP_AXI_WIN(win)	PAB_REG_ADDR(0x4ba4, win)

#define PAB_PEX_AMAP_PEX_WIN_L(win)	PAB_REG_ADDR(0x4ba8, win)

#define PAB_PEX_AMAP_PEX_WIN_H(win)	PAB_REG_ADDR(0x4bac, win)
@@ -462,7 +463,7 @@ static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie) 
}



static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num,

			       u64 pci_addr, u32 type, u64 size)

			       u64 cpu_addr, u64 pci_addr, u32 type, u64 size)

{

	u32 value;

	u64 size64 = ~(size - 1);
@@ -482,7 +483,10 @@ static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num, 
	csr_writel(pcie, upper_32_bits(size64),

		   PAB_EXT_PEX_AMAP_SIZEN(win_num));



	csr_writel(pcie, pci_addr, PAB_PEX_AMAP_AXI_WIN(win_num));

	csr_writel(pcie, lower_32_bits(cpu_addr),

		   PAB_PEX_AMAP_AXI_WIN(win_num));

	csr_writel(pcie, upper_32_bits(cpu_addr),

		   PAB_EXT_PEX_AMAP_AXI_WIN(win_num));



	csr_writel(pcie, lower_32_bits(pci_addr),

		   PAB_PEX_AMAP_PEX_WIN_L(win_num));
@@ -624,7 +628,7 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) 
			   CFG_WINDOW_TYPE, resource_size(pcie->ob_io_res));



	/* memory inbound translation window */

	program_ib_windows(pcie, WIN_NUM_0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);

	program_ib_windows(pcie, WIN_NUM_0, 0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);



	/* Get the I/O and memory ranges from DT */

	resource_list_for_each_entry(win, &pcie->resources) {