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Commit 452420d2 authored by Tvrtko Ursulin's avatar Tvrtko Ursulin
Browse files

drm/i915: Fuse per-context workaround handling with the common framework 



Convert the per context workaround handling code to run against the newly
introduced common workaround framework and fuse the two to use the
existing smarter list add helper, the one which does the sorted insert and
merges registers where possible.

This completes migration of all four classes of workarounds onto the
common framework.

Existing macros are kept untouched for smaller code churn.

v2:
 * Rename to list name ctx_wa_list and move from dev_priv to engine.

v3:
 * API rename and parameters tweaking. (Chris Wilson)

Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20181203133357.10341-1-tvrtko.ursulin@linux.intel.com
parent 69bcdecf

drivers/gpu/drm/i915/i915_debugfs.c

+7 −5
Original line number Diff line number Diff line
@@ -3375,13 +3375,15 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused) 


static int i915_wa_registers(struct seq_file *m, void *unused)

{

	struct i915_workarounds *wa = &node_to_i915(m->private)->workarounds;

	int i;

	struct drm_i915_private *i915 = node_to_i915(m->private);

	const struct i915_wa_list *wal = &i915->engine[RCS]->ctx_wa_list;

	struct i915_wa *wa;

	unsigned int i;



	seq_printf(m, "Workarounds applied: %d\n", wa->count);

	for (i = 0; i < wa->count; ++i)

	seq_printf(m, "Workarounds applied: %u\n", wal->count);

	for (i = 0, wa = wal->list; i < wal->count; i++, wa++)

		seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n",

			   wa->reg[i].addr, wa->reg[i].value, wa->reg[i].mask);

			   i915_mmio_reg_offset(wa->reg), wa->val, wa->mask);



	return 0;

}

drivers/gpu/drm/i915/i915_drv.h

+0 −15
Original line number Diff line number Diff line
@@ -1190,20 +1190,6 @@ struct i915_frontbuffer_tracking { 
	unsigned flip_bits;

};



struct i915_wa_reg {

	u32 addr;

	u32 value;

	/* bitmask representing WA bits */

	u32 mask;

};



#define I915_MAX_WA_REGS 16



struct i915_workarounds {

	struct i915_wa_reg reg[I915_MAX_WA_REGS];

	u32 count;

};



struct i915_virtual_gpu {

	bool active;

	u32 caps;
@@ -1653,7 +1639,6 @@ struct drm_i915_private { 


	int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];



	struct i915_workarounds workarounds;

	struct i915_wa_list gt_wa_list;



	struct i915_frontbuffer_tracking fb_tracking;

drivers/gpu/drm/i915/i915_gem_context.c

+1 −5
Original line number Diff line number Diff line
@@ -535,16 +535,12 @@ static bool needs_preempt_context(struct drm_i915_private *i915) 
int i915_gem_contexts_init(struct drm_i915_private *dev_priv)

{

	struct i915_gem_context *ctx;

	int ret;



	/* Reassure ourselves we are only called once */

	GEM_BUG_ON(dev_priv->kernel_context);

	GEM_BUG_ON(dev_priv->preempt_context);



	ret = intel_ctx_workarounds_init(dev_priv);

	if (ret)

		return ret;



	intel_engine_init_ctx_wa(dev_priv->engine[RCS]);

	init_contexts(dev_priv);



	/* lowest priority; idle task */

drivers/gpu/drm/i915/intel_engine_cs.c

+1 −0
Original line number Diff line number Diff line
@@ -724,6 +724,7 @@ void intel_engine_cleanup_common(struct intel_engine_cs *engine) 


	i915_timeline_fini(&engine->timeline);



	intel_wa_list_free(&engine->ctx_wa_list);

	intel_wa_list_free(&engine->wa_list);

	intel_wa_list_free(&engine->whitelist);

}

drivers/gpu/drm/i915/intel_lrc.c

+1 −1
Original line number Diff line number Diff line
@@ -2087,7 +2087,7 @@ static int gen8_init_rcs_context(struct i915_request *rq) 
{

	int ret;



	ret = intel_ctx_workarounds_emit(rq);

	ret = intel_engine_emit_ctx_wa(rq);

	if (ret)

		return ret;