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Commit 4520e692 authored by Philipp Zabel's avatar Philipp Zabel Committed by Russell King
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ARM: dts: imx6qdl: Add IPU DI ports and endpoints, move imx-drm node to dtsi



This patch connects IPU and display encoder (HDMI, LVDS, MIPI)
device tree nodes, as well as parallel displays on the DISP0
and DISP1 outputs, using the OF graph bindings described in
Documentation/devicetree/bindings/media/video-interfaces.txt

The IPU ports correspond to the two display interfaces. The
order of endpoints in the ports is arbitrary.

Each encoder with an associated input multiplexer has multiple
input ports in the device tree. The order and reg property of
the ports must correspond to the multiplexer input order.

Since the imx-drm node now only needs to contain links to the
display interfaces, it can be moved to the SoC dtsi level. At
the board level, only connections between the display interface
ports and encoders or panels have to be added.

Signed-off-by: default avatarPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent e05c8c9a
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+9 −13
Original line number Diff line number Diff line
@@ -70,6 +70,15 @@
			};
		};
	};

	display-subsystem {
		compatible = "fsl,imx-display-subsystem";
		ports = <&ipu1_di0>, <&ipu1_di1>;
	};
};

&hdmi {
	compatible = "fsl,imx6dl-hdmi";
};

&ldb {
@@ -79,17 +88,4 @@
	clock-names = "di0_pll", "di1_pll",
		      "di0_sel", "di1_sel",
		      "di0", "di1";

	lvds-channel@0 {
		crtcs = <&ipu1 0>, <&ipu1 1>;
	};

	lvds-channel@1 {
		crtcs = <&ipu1 0>, <&ipu1 1>;
	};
};

&hdmi {
	compatible = "fsl,imx6dl-hdmi";
	crtcs = <&ipu1 0>, <&ipu1 1>;
};
+0 −4
Original line number Diff line number Diff line
@@ -20,10 +20,6 @@
	compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
};

&imx_drm {
	crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
};

&sata {
	status = "okay";
};
+118 −6
Original line number Diff line number Diff line
@@ -132,13 +132,84 @@
		};

		ipu2: ipu@02800000 {
			#crtc-cells = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,imx6q-ipu";
			reg = <0x02800000 0x400000>;
			interrupts = <0 8 0x4 0 7 0x4>;
			clocks = <&clks 133>, <&clks 134>, <&clks 137>;
			clock-names = "bus", "di0", "di1";
			resets = <&src 4>;

			ipu2_di0: port@2 {
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <2>;

				ipu2_di0_disp0: endpoint@0 {
				};

				ipu2_di0_hdmi: endpoint@1 {
					remote-endpoint = <&hdmi_mux_2>;
				};

				ipu2_di0_mipi: endpoint@2 {
				};

				ipu2_di0_lvds0: endpoint@3 {
					remote-endpoint = <&lvds0_mux_2>;
				};

				ipu2_di0_lvds1: endpoint@4 {
					remote-endpoint = <&lvds1_mux_2>;
				};
			};

			ipu2_di1: port@3 {
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <3>;

				ipu2_di1_hdmi: endpoint@1 {
					remote-endpoint = <&hdmi_mux_3>;
				};

				ipu2_di1_mipi: endpoint@2 {
				};

				ipu2_di1_lvds0: endpoint@3 {
					remote-endpoint = <&lvds0_mux_3>;
				};

				ipu2_di1_lvds1: endpoint@4 {
					remote-endpoint = <&lvds1_mux_3>;
				};
			};
		};
	};

	display-subsystem {
		compatible = "fsl,imx-display-subsystem";
		ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
	};
};

&hdmi {
	compatible = "fsl,imx6q-hdmi";

	port@2 {
		reg = <2>;

		hdmi_mux_2: endpoint {
			remote-endpoint = <&ipu2_di0_hdmi>;
		};
	};

	port@3 {
		reg = <3>;

		hdmi_mux_3: endpoint {
			remote-endpoint = <&ipu2_di1_hdmi>;
		};
	};
};
@@ -152,15 +223,56 @@
		      "di0", "di1";

	lvds-channel@0 {
		crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
		port@2 {
			reg = <2>;

			lvds0_mux_2: endpoint {
				remote-endpoint = <&ipu2_di0_lvds0>;
			};
		};

		port@3 {
			reg = <3>;

			lvds0_mux_3: endpoint {
				remote-endpoint = <&ipu2_di1_lvds0>;
			};
		};
	};

	lvds-channel@1 {
		crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
		port@2 {
			reg = <2>;

			lvds1_mux_2: endpoint {
				remote-endpoint = <&ipu2_di0_lvds1>;
			};
		};

&hdmi {
	compatible = "fsl,imx6q-hdmi";
	crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
		port@3 {
			reg = <3>;

			lvds1_mux_3: endpoint {
				remote-endpoint = <&ipu2_di1_lvds1>;
			};
		};
	};
};

&mipi_dsi {
	port@2 {
		reg = <2>;

		mipi_mux_2: endpoint {
			remote-endpoint = <&ipu2_di0_mipi>;
		};
	};

	port@3 {
		reg = <3>;

		mipi_mux_3: endpoint {
			remote-endpoint = <&ipu2_di1_mipi>;
		};
	};
};
+0 −6
Original line number Diff line number Diff line
@@ -62,12 +62,6 @@
		};
	};

	imx_drm: imx-drm {
		compatible = "fsl,imx-drm";
		crtcs = <&ipu1 0>, <&ipu1 1>;
		connectors = <&ldb>;
	};

	sound {
		compatible = "fsl,imx6q-sabresd-wm8962",
			   "fsl,imx-audio-wm8962";
+126 −2
Original line number Diff line number Diff line
@@ -1358,23 +1358,77 @@
				status = "disabled";

				lvds-channel@0 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <0>;
					status = "disabled";

					port@0 {
						reg = <0>;

						lvds0_mux_0: endpoint {
							remote-endpoint = <&ipu1_di0_lvds0>;
						};
					};

					port@1 {
						reg = <1>;

						lvds0_mux_1: endpoint {
							remote-endpoint = <&ipu1_di1_lvds0>;
						};
					};
				};

				lvds-channel@1 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <1>;
					status = "disabled";

					port@0 {
						reg = <0>;

						lvds1_mux_0: endpoint {
							remote-endpoint = <&ipu1_di0_lvds1>;
						};
					};

					port@1 {
						reg = <1>;

						lvds1_mux_1: endpoint {
							remote-endpoint = <&ipu1_di1_lvds1>;
						};
					};
				};
			};

			hdmi: hdmi@0120000 {
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x00120000 0x9000>;
				interrupts = <0 115 0x04>;
				gpr = <&gpr>;
				clocks = <&clks 123>, <&clks 124>;
				clock-names = "iahb", "isfr";
				status = "disabled";

				port@0 {
					reg = <0>;

					hdmi_mux_0: endpoint {
						remote-endpoint = <&ipu1_di0_hdmi>;
					};
				};

				port@1 {
					reg = <1>;

					hdmi_mux_1: endpoint {
						remote-endpoint = <&ipu1_di1_hdmi>;
					};
				};
			};

			dcic1: dcic@020e4000 {
@@ -1588,8 +1642,27 @@
				reg = <0x021dc000 0x4000>;
			};

			mipi@021e0000 { /* MIPI-DSI */
			mipi_dsi: mipi@021e0000 {
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x021e0000 0x4000>;
				status = "disabled";

				port@0 {
					reg = <0>;

					mipi_mux_0: endpoint {
						remote-endpoint = <&ipu1_di0_mipi>;
					};
				};

				port@1 {
					reg = <1>;

					mipi_mux_1: endpoint {
						remote-endpoint = <&ipu1_di1_mipi>;
					};
				};
			};

			vdoa@021e4000 {
@@ -1643,13 +1716,64 @@
		};

		ipu1: ipu@02400000 {
			#crtc-cells = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,imx6q-ipu";
			reg = <0x02400000 0x400000>;
			interrupts = <0 6 0x4 0 5 0x4>;
			clocks = <&clks 130>, <&clks 131>, <&clks 132>;
			clock-names = "bus", "di0", "di1";
			resets = <&src 2>;

			ipu1_di0: port@2 {
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <2>;

				ipu1_di0_disp0: endpoint@0 {
				};

				ipu1_di0_hdmi: endpoint@1 {
					remote-endpoint = <&hdmi_mux_0>;
				};

				ipu1_di0_mipi: endpoint@2 {
					remote-endpoint = <&mipi_mux_0>;
				};

				ipu1_di0_lvds0: endpoint@3 {
					remote-endpoint = <&lvds0_mux_0>;
				};

				ipu1_di0_lvds1: endpoint@4 {
					remote-endpoint = <&lvds1_mux_0>;
				};
			};

			ipu1_di1: port@3 {
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <3>;

				ipu1_di0_disp1: endpoint@0 {
				};

				ipu1_di1_hdmi: endpoint@1 {
					remote-endpoint = <&hdmi_mux_1>;
				};

				ipu1_di1_mipi: endpoint@2 {
					remote-endpoint = <&mipi_mux_1>;
				};

				ipu1_di1_lvds0: endpoint@3 {
					remote-endpoint = <&lvds0_mux_1>;
				};

				ipu1_di1_lvds1: endpoint@4 {
					remote-endpoint = <&lvds1_mux_1>;
				};
			};
		};
	};
};