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Commit 451a59bd authored by Linus Walleij's avatar Linus Walleij
Browse files

Merge tag 'intel-pinctrl-fixes-v5.4-2' of... 

Merge tag 'intel-pinctrl-fixes-v5.4-2' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into fixes

intel-pinctrl fixes for v5.4 part 2

A couple more fixes for Intel pinctrl drivers:

  - Try to avoid glitches when pin is in GPIO mode
  - Fix cherryview irq_valid_mask calculation
  - Allocate cherryview IRQ chip dynamically to avoid triggering warning
    from GPIO core
parents d6d5df1d 67d33aec

drivers/pinctrl/intel/pinctrl-cherryview.c

+13 −13
Original line number Diff line number Diff line
@@ -147,6 +147,7 @@ struct chv_pin_context { 
 * @pctldesc: Pin controller description

 * @pctldev: Pointer to the pin controller device

 * @chip: GPIO chip in this pin controller

 * @irqchip: IRQ chip in this pin controller

 * @regs: MMIO registers

 * @intr_lines: Stores mapping between 16 HW interrupt wires and GPIO

 *		offset (in GPIO number space)
@@ -162,6 +163,7 @@ struct chv_pinctrl { 
	struct pinctrl_desc pctldesc;

	struct pinctrl_dev *pctldev;

	struct gpio_chip chip;

	struct irq_chip irqchip;

	void __iomem *regs;

	unsigned intr_lines[16];

	const struct chv_community *community;
@@ -1466,16 +1468,6 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned int type) 
	return 0;

}



static struct irq_chip chv_gpio_irqchip = {

	.name = "chv-gpio",

	.irq_startup = chv_gpio_irq_startup,

	.irq_ack = chv_gpio_irq_ack,

	.irq_mask = chv_gpio_irq_mask,

	.irq_unmask = chv_gpio_irq_unmask,

	.irq_set_type = chv_gpio_irq_type,

	.flags = IRQCHIP_SKIP_SET_WAKE,

};



static void chv_gpio_irq_handler(struct irq_desc *desc)

{

	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
@@ -1559,7 +1551,7 @@ static void chv_init_irq_valid_mask(struct gpio_chip *chip, 
		intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;



		if (intsel >= community->nirqs)

			clear_bit(i, valid_mask);

			clear_bit(desc->number, valid_mask);

	}

}
@@ -1625,7 +1617,15 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) 
		}

	}



	ret = gpiochip_irqchip_add(chip, &chv_gpio_irqchip, 0,

	pctrl->irqchip.name = "chv-gpio";

	pctrl->irqchip.irq_startup = chv_gpio_irq_startup;

	pctrl->irqchip.irq_ack = chv_gpio_irq_ack;

	pctrl->irqchip.irq_mask = chv_gpio_irq_mask;

	pctrl->irqchip.irq_unmask = chv_gpio_irq_unmask;

	pctrl->irqchip.irq_set_type = chv_gpio_irq_type;

	pctrl->irqchip.flags = IRQCHIP_SKIP_SET_WAKE;



	ret = gpiochip_irqchip_add(chip, &pctrl->irqchip, 0,

				   handle_bad_irq, IRQ_TYPE_NONE);

	if (ret) {

		dev_err(pctrl->dev, "failed to add IRQ chip\n");
@@ -1642,7 +1642,7 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) 
		}

	}



	gpiochip_set_chained_irqchip(chip, &chv_gpio_irqchip, irq,

	gpiochip_set_chained_irqchip(chip, &pctrl->irqchip, irq,

				     chv_gpio_irq_handler);

	return 0;

}

drivers/pinctrl/intel/pinctrl-intel.c

+20 −1
Original line number Diff line number Diff line
@@ -52,6 +52,7 @@ 
#define PADCFG0_GPIROUTNMI		BIT(17)

#define PADCFG0_PMODE_SHIFT		10

#define PADCFG0_PMODE_MASK		GENMASK(13, 10)

#define PADCFG0_PMODE_GPIO		0

#define PADCFG0_GPIORXDIS		BIT(9)

#define PADCFG0_GPIOTXDIS		BIT(8)

#define PADCFG0_GPIORXSTATE		BIT(1)
@@ -332,7 +333,7 @@ static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 
	cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));



	mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;

	if (!mode)

	if (mode == PADCFG0_PMODE_GPIO)

		seq_puts(s, "GPIO ");

	else

		seq_printf(s, "mode %d ", mode);
@@ -458,6 +459,11 @@ static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input) 
	writel(value, padcfg0);

}



static int intel_gpio_get_gpio_mode(void __iomem *padcfg0)

{

	return (readl(padcfg0) & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;

}



static void intel_gpio_set_gpio_mode(void __iomem *padcfg0)

{

	u32 value;
@@ -491,7 +497,20 @@ static int intel_gpio_request_enable(struct pinctrl_dev *pctldev, 
	}



	padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);



	/*

	 * If pin is already configured in GPIO mode, we assume that

	 * firmware provides correct settings. In such case we avoid

	 * potential glitches on the pin. Otherwise, for the pin in

	 * alternative mode, consumer has to supply respective flags.

	 */

	if (intel_gpio_get_gpio_mode(padcfg0) == PADCFG0_PMODE_GPIO) {

		raw_spin_unlock_irqrestore(&pctrl->lock, flags);

		return 0;

	}



	intel_gpio_set_gpio_mode(padcfg0);



	/* Disable TX buffer and enable RX (this will be input) */

	__intel_gpio_set_direction(padcfg0, true);