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Commit 44de3395 authored by Alex Nixon's avatar Alex Nixon Committed by Konrad Rzeszutek Wilk
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x86/PCI: Clean up pci_cache_line_size 



Separate out x86 cache_line_size initialisation code into its own
function (so it can be shared by Xen later in this patch series)

[ Impact: cleanup ]

Signed-off-by: default avatarAlex Nixon <alex.nixon@citrix.com>
Signed-off-by: default avatarJeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>
Signed-off-by: default avatarKonrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Reviewed-by: default avatar"H. Peter Anvin" <hpa@zytor.com>
Reviewed-by: default avatarMatthew Wilcox <willy@linux.intel.com>
Reviewed-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Cc: x86@kernel.org
parent 15ebbb82

arch/x86/include/asm/pci_x86.h

+1 −0
Original line number Diff line number Diff line
@@ -47,6 +47,7 @@ enum pci_bf_sort_state { 
extern unsigned int pcibios_max_latency;



void pcibios_resource_survey(void);

void pcibios_set_cache_line_size(void);



/* pci-pc.c */

arch/x86/pci/common.c

+10 −7
Original line number Diff line number Diff line
@@ -421,16 +421,10 @@ struct pci_bus * __devinit pcibios_scan_root(int busnum) 


	return bus;

}



int __init pcibios_init(void)

void __init pcibios_set_cache_line_size(void)

{

	struct cpuinfo_x86 *c = &boot_cpu_data;



	if (!raw_pci_ops) {

		printk(KERN_WARNING "PCI: System does not support PCI\n");

		return 0;

	}



	/*

	 * Set PCI cacheline size to that of the CPU if the CPU has reported it.

	 * (For older CPUs that don't support cpuid, we se it to 32 bytes
@@ -445,7 +439,16 @@ int __init pcibios_init(void) 
 		pci_dfl_cache_line_size = 32 >> 2;

		printk(KERN_DEBUG "PCI: Unknown cacheline size. Setting to 32 bytes\n");

	}

}



int __init pcibios_init(void)

{

	if (!raw_pci_ops) {

		printk(KERN_WARNING "PCI: System does not support PCI\n");

		return 0;

	}



	pcibios_set_cache_line_size();

	pcibios_resource_survey();



	if (pci_bf_sort >= pci_force_bf)