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Commit 44224bdb authored by John David Anglin's avatar John David Anglin Committed by Helge Deller
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parisc: Add memory clobber to TLB purges 



The pdtlb and pitlb instructions are strongly ordered. The asms invoking
these instructions should be compiler memory barriers to ensure the
compiler doesn't reorder memory operations around these instructions.

Signed-off-by: default avatarJohn David Anglin <dave.anglin@bell.net>
CC: stable@vger.kernel.org # v4.20+
Fixes: 3847dab7 ("parisc: Add alternative coding infrastructure")
Signed-off-by: default avatarHelge Deller <deller@gmx.de>
parent 9e5c6021

arch/parisc/include/asm/cache.h

+3 −3
Original line number Diff line number Diff line
@@ -44,14 +44,14 @@ void parisc_setup_cache_timing(void); 


#define pdtlb(addr)	asm volatile("pdtlb 0(%%sr1,%0)" \

			ALTERNATIVE(ALT_COND_NO_SMP, INSN_PxTLB) \

			: : "r" (addr))

			: : "r" (addr) : "memory")

#define pitlb(addr)	asm volatile("pitlb 0(%%sr1,%0)" \

			ALTERNATIVE(ALT_COND_NO_SMP, INSN_PxTLB) \

			ALTERNATIVE(ALT_COND_NO_SPLIT_TLB, INSN_NOP) \

			: : "r" (addr))

			: : "r" (addr) : "memory")

#define pdtlb_kernel(addr)  asm volatile("pdtlb 0(%0)"   \

			ALTERNATIVE(ALT_COND_NO_SMP, INSN_PxTLB) \

			: : "r" (addr))

			: : "r" (addr) : "memory")



#define asm_io_fdc(addr) asm volatile("fdc %%r0(%0)" \

			ALTERNATIVE(ALT_COND_NO_DCACHE, INSN_NOP) \