Commit 4419e19d authored Aug 15, 2019 by Anson Huang Committed by Daniel Lezcano Aug 27, 2019

clocksource/drivers/imx-sysctr: Add internal clock divider handle



The system counter block guide states that the base clock is
internally divided by 3 before use, that means the clock input of
system counter defined in DT should be base clock which is normally
from OSC, and then internally divided by 3 before use.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>

parent 1ce861ce

drivers/clocksource/timer-imx-sysctr.c

+5 −0

Original line number	Diff line number	Diff line
		@@ -20,6 +20,8 @@
		#define SYS_CTR_EN 0x1
		#define SYS_CTR_IRQ_MASK 0x2

		#define SYS_CTR_CLK_DIV 0x3

		static void __iomem *sys_ctr_base;
		static u32 cmpcr;

		@@ -134,6 +136,9 @@ static int __init sysctr_timer_init(struct device_node *np)
		if (ret)
		return ret;

		/* system counter clock is divided by 3 internally */
		to_sysctr.of_clk.rate /= SYS_CTR_CLK_DIV;

		sys_ctr_base = timer_of_base(&to_sysctr);
		cmpcr = readl(sys_ctr_base + CMPCR);
		cmpcr &= ~SYS_CTR_EN;