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Commit 440f136b authored by Michal Wajdeczko's avatar Michal Wajdeczko Committed by Chris Wilson
Browse files

drm/i915/guc: Update GuC CTB response definition 



Current GuC firmwares identify response message in a different way.

v2: update comments for other H2G bits (Daniele)

Signed-off-by: default avatarMichal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Kelvin Gardiner <kelvin.gardiner@intel.com>
Cc: John Spotswood <john.a.spotswood@intel.com>
Reviewed-by: default avatarDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190527183613.17076-14-michal.wajdeczko@intel.com
parent 54c52a84

drivers/gpu/drm/i915/intel_guc_ct.c

+1 −1
Original line number Diff line number Diff line
@@ -565,7 +565,7 @@ static inline unsigned int ct_header_get_action(u32 header) 


static inline bool ct_header_is_response(u32 header)

{

	return ct_header_get_action(header) == INTEL_GUC_ACTION_DEFAULT;

	return !!(header & GUC_CT_MSG_IS_RESPONSE);

}



static int ctb_read(struct intel_guc_ct_buffer *ctb, u32 *data)

drivers/gpu/drm/i915/intel_guc_fwif.h

+5 −3
Original line number Diff line number Diff line
@@ -355,14 +355,16 @@ struct guc_ct_buffer_desc { 
 *

 * bit[4..0]	message len (in dwords)

 * bit[7..5]	reserved

 * bit[8]	write fence to desc

 * bit[9]	write status to H2G buff

 * bit[10]	send status (via G2H)

 * bit[8]	response (G2H only)

 * bit[8]	write fence to desc (H2G only)

 * bit[9]	write status to H2G buff (H2G only)

 * bit[10]	send status back via G2H (H2G only)

 * bit[15..11]	reserved

 * bit[31..16]	action code

 */

#define GUC_CT_MSG_LEN_SHIFT			0

#define GUC_CT_MSG_LEN_MASK			0x1F

#define GUC_CT_MSG_IS_RESPONSE			(1 << 8)

#define GUC_CT_MSG_WRITE_FENCE_TO_DESC		(1 << 8)

#define GUC_CT_MSG_WRITE_STATUS_TO_BUFF		(1 << 9)

#define GUC_CT_MSG_SEND_STATUS			(1 << 10)