media: tc358743: Increase FIFO trigger level to 374

	state->pdata.refclk_hz = clk_get_rate(refclk);

	state->pdata.ddc5v_delay = DDC5V_DELAY_100_MS;

	state->pdata.enable_hdcp = false;

	/* A FIFO level of 16 should be enough for 2-lane 720p60 at 594 MHz. */

	state->pdata.fifo_level = 16;

	/*

	 * Ideally the FIFO trigger level should be set based on the input and

	 * output data rates, but the calculations required are buried in

	 * Toshiba's register settings spreadsheet.

	 * A value of 16 works with a 594Mbps data rate for 720p60 (using 2

	 * lanes) and 1080p60 (using 4 lanes), but fails when the data rate

	 * is increased, or a lower pixel clock is used that result in CSI

	 * reading out faster than the data is arriving.

	 *

	 * A value of 374 works with both those modes at 594Mbps, and with most

	 * modes on 972Mbps.

	 */

	state->pdata.fifo_level = 374;

	/*

	 * The PLL input clock is obtained by dividing refclk by pll_prd.

	 * It must be between 6 MHz and 40 MHz, lower frequency is better.