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Commit 43c95d36 authored by Linus Torvalds's avatar Linus Torvalds
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Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes for the v5.3 kernel cycle:

  Core changes:

   - Device links can optionally be added between a pin control producer
     and its consumers. This will affect how the system power management
     is handled: a pin controller will not suspend before all of its
     consumers have been suspended.

     This was necessary for the ST Microelectronics STMFX expander and
     need to be tested on other systems as well: it makes sense to make
     this default in the long run.

     Right now it is opt-in per driver.

   - Drive strength can be specified in microamps. With decreases in
     silicon technology, milliamps isn't granular enough, let's make it
     possible to select drive strengths in microamps.

     Right now the Meson (AMlogic) driver needs this.

  New drivers:

   - New subdriver for the Tegra 194 SoC.

   - New subdriver for the Qualcomm SDM845.

   - New subdriver for the Qualcomm SM8150.

   - New subdriver for the Freescale i.MX8MN (Freescale is now a product
     line of NXP).

   - New subdriver for Marvell MV98DX1135.

  Driver improvements:

   - The Bitmain BM1880 driver now supports pin config in addition to
     muxing.

   - The Qualcomm drivers can now reserve some GPIOs as taken aside and
     not usable for users. This is used in ACPI systems to take out some
     GPIO lines used by the BIOS so that noone else (neither kernel nor
     userspace) will play with them by mistake and crash the machine.

   - A slew of refurbishing around the Aspeed drivers (board management
     controllers for servers) in preparation for the new Aspeed AST2600
     SoC.

   - A slew of improvements over the SH PFC drivers as usual.

   - Misc cleanups and fixes"

* tag 'pinctrl-v5.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (106 commits)
  pinctrl: aspeed: Strip moved macros and structs from private header
  pinctrl: aspeed: Fix missed include
  pinctrl: baytrail: Use GENMASK() consistently
  pinctrl: baytrail: Re-use data structures from pinctrl-intel.h
  pinctrl: baytrail: Use defined macro instead of magic in byt_get_gpio_mux()
  pinctrl: qcom: Add SM8150 pinctrl driver
  dt-bindings: pinctrl: qcom: Add SM8150 pinctrl binding
  dt-bindings: pinctrl: qcom: Document missing gpio nodes
  pinctrl: aspeed: Add implementation-related documentation
  pinctrl: aspeed: Split out pinmux from general pinctrl
  pinctrl: aspeed: Clarify comment about strapping W1C
  pinctrl: aspeed: Correct comment that is no longer true
  MAINTAINERS: Add entry for ASPEED pinctrl drivers
  dt-bindings: pinctrl: aspeed: Convert AST2500 bindings to json-schema
  dt-bindings: pinctrl: aspeed: Convert AST2400 bindings to json-schema
  dt-bindings: pinctrl: aspeed: Split bindings document in two
  pinctrl: qcom: Add irq_enable callback for msm gpio
  pinctrl: madera: Fixup SPDX headers
  pinctrl: qcom: sdm845: Fix CONFIG preprocessor guard
  pinctrl: tegra: Add bitmask support for parked bits
  ...
parents 073c916b 4c105769
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+2 −0
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@@ -24,6 +24,8 @@ Required properties:
  "allwinner,sun8i-h3-pinctrl"
  "allwinner,sun8i-h3-r-pinctrl"
  "allwinner,sun8i-r40-pinctrl"
  "allwinner,sun8i-v3-pinctrl"
  "allwinner,sun8i-v3s-pinctrl"
  "allwinner,sun50i-a64-pinctrl"
  "allwinner,sun50i-a64-r-pinctrl"
  "allwinner,sun50i-h5-pinctrl"
+81 −0
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# SPDX-License-Identifier: GPL-2.0-or-later
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/aspeed,ast2400-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ASPEED AST2400 Pin Controller

maintainers:
  - Andrew Jeffery <andrew@aj.id.au>

description: |+
  The pin controller node should be the child of a syscon node with the
  required property:

  - compatible:     Should be one of the following:
                    "aspeed,ast2400-scu", "syscon", "simple-mfd"
                    "aspeed,g4-scu", "syscon", "simple-mfd"

  Refer to the the bindings described in
  Documentation/devicetree/bindings/mfd/syscon.txt

properties:
  compatible:
    enum: [ aspeed,ast2400-pinctrl, aspeed,g4-pinctrl ]

patternProperties:
  '^.*$':
    if:
      type: object
    then:
      patternProperties:
        "^function|groups$":
          allOf:
            - $ref: "/schemas/types.yaml#/definitions/string"
            - enum: [ "ACPI", "ADC0", "ADC1", "ADC10", "ADC11", "ADC12", "ADC13",
              "ADC14", "ADC15", "ADC2", "ADC3", "ADC4", "ADC5", "ADC6", "ADC7",
              "ADC8", "ADC9", "BMCINT", "DDCCLK", "DDCDAT", "EXTRST", "FLACK",
              "FLBUSY", "FLWP", "GPID", "GPID0", "GPID2", "GPID4", "GPID6",
              "GPIE0", "GPIE2", "GPIE4", "GPIE6", "I2C10", "I2C11", "I2C12",
              "I2C13", "I2C14", "I2C3", "I2C4", "I2C5", "I2C6", "I2C7", "I2C8",
              "I2C9", "LPCPD", "LPCPME", "LPCRST", "LPCSMI", "MAC1LINK",
              "MAC2LINK", "MDIO1", "MDIO2", "NCTS1", "NCTS2", "NCTS3", "NCTS4",
              "NDCD1", "NDCD2", "NDCD3", "NDCD4", "NDSR1", "NDSR2", "NDSR3",
              "NDSR4", "NDTR1", "NDTR2", "NDTR3", "NDTR4", "NDTS4", "NRI1",
              "NRI2", "NRI3", "NRI4", "NRTS1", "NRTS2", "NRTS3", "OSCCLK",
              "PWM0", "PWM1", "PWM2", "PWM3", "PWM4", "PWM5", "PWM6", "PWM7",
              "RGMII1", "RGMII2", "RMII1", "RMII2", "ROM16", "ROM8", "ROMCS1",
              "ROMCS2", "ROMCS3", "ROMCS4", "RXD1", "RXD2", "RXD3", "RXD4",
              "SALT1", "SALT2", "SALT3", "SALT4", "SD1", "SD2", "SGPMCK",
              "SGPMI", "SGPMLD", "SGPMO", "SGPSCK", "SGPSI0", "SGPSI1", "SGPSLD",
              "SIOONCTRL", "SIOPBI", "SIOPBO", "SIOPWREQ", "SIOPWRGD", "SIOS3",
              "SIOS5", "SIOSCI", "SPI1", "SPI1DEBUG", "SPI1PASSTHRU", "SPICS1",
              "TIMER3", "TIMER4", "TIMER5", "TIMER6", "TIMER7", "TIMER8", "TXD1",
              "TXD2", "TXD3", "TXD4", "UART6", "USB11D1", "USB11H2", "USB2D1",
              "USB2H1", "USBCKI", "VGABIOS_ROM", "VGAHS", "VGAVS", "VPI18",
              "VPI24", "VPI30", "VPO12", "VPO24", "WDTRST1", "WDTRST2" ]

required:
  - compatible

examples:
  - |
    syscon: scu@1e6e2000 {
        compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
        reg = <0x1e6e2000 0x1a8>;

        pinctrl: pinctrl {
            compatible = "aspeed,g4-pinctrl";

            pinctrl_i2c3_default: i2c3_default {
                function = "I2C3";
                groups = "I2C3";
            };

            pinctrl_gpioh0_unbiased_default: gpioh0 {
                pins = "A8";
                bias-disable;
            };
        };
    };
+134 −0
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# SPDX-License-Identifier: GPL-2.0-or-later
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/aspeed,ast2500-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ASPEED AST2500 Pin Controller

maintainers:
  - Andrew Jeffery <andrew@aj.id.au>

description: |+
  The pin controller node should be the child of a syscon node with the
  required property:

  - compatible: 	Should be one of the following:
  			"aspeed,ast2500-scu", "syscon", "simple-mfd"
  			"aspeed,g5-scu", "syscon", "simple-mfd"

  Refer to the the bindings described in
  Documentation/devicetree/bindings/mfd/syscon.txt

properties:
  compatible:
    enum: [ aspeed,ast2500-pinctrl, aspeed,g5-pinctrl ]
  aspeed,external-nodes:
    minItems: 2
    maxItems: 2
    allOf:
      - $ref: /schemas/types.yaml#/definitions/phandle-array
    description: |
      A cell of phandles to external controller nodes:
      0: compatible with "aspeed,ast2500-gfx", "syscon"
      1: compatible with "aspeed,ast2500-lhc", "syscon"

patternProperties:
  '^.*$':
    if:
      type: object
    then:
      patternProperties:
        "^function|groups$":
          allOf:
            - $ref: "/schemas/types.yaml#/definitions/string"
            - enum: [ "ACPI", "ADC0", "ADC1", "ADC10", "ADC11", "ADC12", "ADC13",
              "ADC14", "ADC15", "ADC2", "ADC3", "ADC4", "ADC5", "ADC6", "ADC7",
              "ADC8", "ADC9", "BMCINT", "DDCCLK", "DDCDAT", "ESPI", "FWSPICS1",
              "FWSPICS2", "GPID0", "GPID2", "GPID4", "GPID6", "GPIE0", "GPIE2",
              "GPIE4", "GPIE6", "I2C10", "I2C11", "I2C12", "I2C13", "I2C14",
              "I2C3", "I2C4", "I2C5", "I2C6", "I2C7", "I2C8", "I2C9", "LAD0",
              "LAD1", "LAD2", "LAD3", "LCLK", "LFRAME", "LPCHC", "LPCPD",
              "LPCPLUS", "LPCPME", "LPCRST", "LPCSMI", "LSIRQ", "MAC1LINK",
              "MAC2LINK", "MDIO1", "MDIO2", "NCTS1", "NCTS2", "NCTS3", "NCTS4",
              "NDCD1", "NDCD2", "NDCD3", "NDCD4", "NDSR1", "NDSR2", "NDSR3",
              "NDSR4", "NDTR1", "NDTR2", "NDTR3", "NDTR4", "NRI1", "NRI2",
              "NRI3", "NRI4", "NRTS1", "NRTS2", "NRTS3", "NRTS4", "OSCCLK",
              "PEWAKE", "PNOR", "PWM0", "PWM1", "PWM2", "PWM3", "PWM4", "PWM5",
              "PWM6", "PWM7", "RGMII1", "RGMII2", "RMII1", "RMII2", "RXD1",
              "RXD2", "RXD3", "RXD4", "SALT1", "SALT10", "SALT11", "SALT12",
              "SALT13", "SALT14", "SALT2", "SALT3", "SALT4", "SALT5", "SALT6",
              "SALT7", "SALT8", "SALT9", "SCL1", "SCL2", "SD1", "SD2", "SDA1",
              "SDA2", "SGPS1", "SGPS2", "SIOONCTRL", "SIOPBI", "SIOPBO",
              "SIOPWREQ", "SIOPWRGD", "SIOS3", "SIOS5", "SIOSCI", "SPI1",
              "SPI1CS1", "SPI1DEBUG", "SPI1PASSTHRU", "SPI2CK", "SPI2CS0",
              "SPI2CS1", "SPI2MISO", "SPI2MOSI", "TIMER3", "TIMER4", "TIMER5",
              "TIMER6", "TIMER7", "TIMER8", "TXD1", "TXD2", "TXD3", "TXD4",
              "UART6", "USB11BHID", "USB2AD", "USB2AH", "USB2BD", "USB2BH",
              "USBCKI", "VGABIOSROM", "VGAHS", "VGAVS", "VPI24", "VPO",
              "WDTRST1", "WDTRST2", ]

required:
  - compatible
  - aspeed,external-nodes

examples:
  - |
    compatible = "simple-bus";
    ranges;

    apb {
        compatible = "simple-bus";
        #address-cells = <1>;
        #size-cells = <1>;
        ranges;

        syscon: scu@1e6e2000 {
            compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
            reg = <0x1e6e2000 0x1a8>;

            pinctrl: pinctrl {
                compatible = "aspeed,g5-pinctrl";
                aspeed,external-nodes = <&gfx &lhc>;

                pinctrl_i2c3_default: i2c3_default {
                    function = "I2C3";
                    groups = "I2C3";
                };

                pinctrl_gpioh0_unbiased_default: gpioh0 {
                    pins = "A18";
                    bias-disable;
                };
            };
        };

        gfx: display@1e6e6000 {
            compatible = "aspeed,ast2500-gfx", "syscon";
            reg = <0x1e6e6000 0x1000>;
        };
    };

    lpc: lpc@1e789000 {
        compatible = "aspeed,ast2500-lpc", "simple-mfd";
        reg = <0x1e789000 0x1000>;

        #address-cells = <1>;
        #size-cells = <1>;
        ranges = <0x0 0x1e789000 0x1000>;

        lpc_host: lpc-host@80 {
            compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
            reg = <0x80 0x1e0>;
            reg-io-width = <4>;

            #address-cells = <1>;
            #size-cells = <1>;
            ranges = <0x0 0x80 0x1e0>;

            lhc: lhc@20 {
                   compatible = "aspeed,ast2500-lhc";
                   reg = <0x20 0x24 0x48 0x8>;
            };
        };
    };
+31 −3
Original line number Diff line number Diff line
@@ -14,7 +14,8 @@ phrase "pin configuration node".
The pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration for BM1880 SoC
includes only pinmux as there is no pinconf support available in SoC.
includes pinmux and various pin configuration parameters, such as pull-up,
slew rate etc...

Each configuration node can consist of multiple nodes describing the pinmux
options. The name of each subnode is not important; all subnodes should be
@@ -84,10 +85,37 @@ Required Properties:
                  gpio66, gpio67, eth1, i2s0, i2s0_mclkin, i2s1, i2s1_mclkin,
                  spi0

Optional Properties:

- bias-disable:  No arguments. Disable pin bias.
- bias-pull-down: No arguments. The specified pins should be configured as
                  pull down.
- bias-pull-up:   No arguments. The specified pins should be configured as
                  pull up.
- input-schmitt-enable: No arguments: Enable schmitt trigger for the specified
                  pins
- input-schmitt-disable: No arguments: Disable schmitt trigger for the specified
                  pins
- slew-rate:      Integer. Sets slew rate for the specified pins.
                  Valid values are:
                  <0>  - Slow
                  <1>  - Fast
- drive-strength: Integer. Selects the drive strength for the specified
                  pins in mA.
                  Valid values are:
                  <4>
                  <8>
                  <12>
                  <16>
                  <20>
                  <24>
                  <28>
                  <32>

Example:
        pinctrl: pinctrl@50 {
        pinctrl: pinctrl@400 {
                compatible = "bitmain,bm1880-pinctrl";
                reg = <0x50 0x4B0>;
                reg = <0x400 0x120>;

                pinctrl_uart0_default: uart0-default {
                        pinmux {
+3 −0
Original line number Diff line number Diff line
@@ -5,6 +5,9 @@ controller, and pinmux/control device.

Required properties:
- compatible: "brcm,bcm2835-gpio"
- compatible: should be one of:
  "brcm,bcm2835-gpio" - BCM2835 compatible pinctrl
  "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
- reg: Should contain the physical address of the GPIO module's registers.
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells : Should be two. The first cell is the pin number and the
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