Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 43b8e1f0 authored by Dave Martin's avatar Dave Martin Committed by Marc Zyngier
Browse files

KVM: arm64: Clarify access behaviour for out-of-range SVE register slice IDs 



The existing documentation for which SVE register slice IDs are
considered out-of-range, and what happens when userspace tries to
access them, is cryptic.

This patch rewords the text with the aim of making it a bit easier to
understand.

No functional change.

Suggested-by: default avatarAndrew Jones <drjones@redhat.com>
Signed-off-by: default avatarDave Martin <Dave.Martin@arm.com>
Reviewed-by: default avatarAndrew Jones <drjones@redhat.com>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
parent fe365b4e

Documentation/virtual/kvm/api.txt

+3 −2
Original line number Diff line number Diff line
@@ -2159,8 +2159,9 @@ arm64 SVE registers have the following bit patterns: 
  0x6050 0000 0015 060 <slice:5>        FFR bits[256*slice + 255 : 256*slice]

  0x6060 0000 0015 ffff                 KVM_REG_ARM64_SVE_VLS pseudo-register



Access to slices beyond the maximum vector length configured for the

vcpu (i.e., where 16 * slice >= max_vq (**)) will fail with ENOENT.

Access to register IDs where 2048 * slice >= 128 * max_vq will fail with

ENOENT.  max_vq is the vcpu's maximum supported vector length in 128-bit

quadwords: see (**) below.



These registers are only accessible on vcpus for which SVE is enabled.

See KVM_ARM_VCPU_INIT for details.