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Commit 4398f31c authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'x86-fixes-for-linus' of... 

Merge branch 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip

* 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
  x86: Fix jump label with RO/NX module protection crash
  x86, hotplug: Fix powersavings with offlined cores on AMD
  x86, mcheck, therm_throt.c: Export symbol platform_thermal_notify to allow coretemp to handler intr
  x86: Use asm-generic/cacheflush.h
  x86: Update CPU cache attributes table descriptors
parents d315777b 89696913

arch/x86/include/asm/cacheflush.h

+1 −41
Original line number Diff line number Diff line 
#ifndef _ASM_X86_CACHEFLUSH_H

#define _ASM_X86_CACHEFLUSH_H



/* Keep includes the same across arches.  */

#include <linux/mm.h>



/* Caches aren't brain-dead on the intel. */

static inline void flush_cache_all(void) { }

static inline void flush_cache_mm(struct mm_struct *mm) { }

static inline void flush_cache_dup_mm(struct mm_struct *mm) { }

static inline void flush_cache_range(struct vm_area_struct *vma,

				     unsigned long start, unsigned long end) { }

static inline void flush_cache_page(struct vm_area_struct *vma,

				    unsigned long vmaddr, unsigned long pfn) { }

#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0

static inline void flush_dcache_page(struct page *page) { }

static inline void flush_dcache_mmap_lock(struct address_space *mapping) { }

static inline void flush_dcache_mmap_unlock(struct address_space *mapping) { }

static inline void flush_icache_range(unsigned long start,

				      unsigned long end) { }

static inline void flush_icache_page(struct vm_area_struct *vma,

				     struct page *page) { }

static inline void flush_icache_user_range(struct vm_area_struct *vma,

					   struct page *page,

					   unsigned long addr,

					   unsigned long len) { }

static inline void flush_cache_vmap(unsigned long start, unsigned long end) { }

static inline void flush_cache_vunmap(unsigned long start,

				      unsigned long end) { }



static inline void copy_to_user_page(struct vm_area_struct *vma,

				     struct page *page, unsigned long vaddr,

				     void *dst, const void *src,

				     unsigned long len)

{

	memcpy(dst, src, len);

}



static inline void copy_from_user_page(struct vm_area_struct *vma,

				       struct page *page, unsigned long vaddr,

				       void *dst, const void *src,

				       unsigned long len)

{

	memcpy(dst, src, len);

}

#include <asm-generic/cacheflush.h>



#ifdef CONFIG_X86_PAT

/*

arch/x86/include/asm/cpu.h

+1 −0
Original line number Diff line number Diff line
@@ -32,5 +32,6 @@ extern void arch_unregister_cpu(int); 


DECLARE_PER_CPU(int, cpu_state);



int __cpuinit mwait_usable(const struct cpuinfo_x86 *);



#endif /* _ASM_X86_CPU_H */

arch/x86/include/asm/jump_label.h

+1 −1
Original line number Diff line number Diff line
@@ -14,7 +14,7 @@ 
	do {							\

		asm goto("1:"					\

			JUMP_LABEL_INITIAL_NOP			\

			".pushsection __jump_table,  \"a\" \n\t"\

			".pushsection __jump_table,  \"aw\" \n\t"\

			_ASM_PTR "1b, %l[" #label "], %c0 \n\t" \

			".popsection \n\t"			\

			: :  "i" (key) :  : label);		\

arch/x86/kernel/cpu/intel_cacheinfo.c

+3 −0
Original line number Diff line number Diff line
@@ -45,6 +45,7 @@ static const struct _cache_table __cpuinitconst cache_table[] = 
	{ 0x0a, LVL_1_DATA, 8 },	/* 2 way set assoc, 32 byte line size */

	{ 0x0c, LVL_1_DATA, 16 },	/* 4-way set assoc, 32 byte line size */

	{ 0x0d, LVL_1_DATA, 16 },	/* 4-way set assoc, 64 byte line size */

	{ 0x0e, LVL_1_DATA, 24 },	/* 6-way set assoc, 64 byte line size */

	{ 0x21, LVL_2,      256 },	/* 8-way set assoc, 64 byte line size */

	{ 0x22, LVL_3,      512 },	/* 4-way set assoc, sectored cache, 64 byte line size */

	{ 0x23, LVL_3,      MB(1) },	/* 8-way set assoc, sectored cache, 64 byte line size */
@@ -66,6 +67,7 @@ static const struct _cache_table __cpuinitconst cache_table[] = 
	{ 0x45, LVL_2,      MB(2) },	/* 4-way set assoc, 32 byte line size */

	{ 0x46, LVL_3,      MB(4) },	/* 4-way set assoc, 64 byte line size */

	{ 0x47, LVL_3,      MB(8) },	/* 8-way set assoc, 64 byte line size */

	{ 0x48, LVL_2,      MB(3) },	/* 12-way set assoc, 64 byte line size */

	{ 0x49, LVL_3,      MB(4) },	/* 16-way set assoc, 64 byte line size */

	{ 0x4a, LVL_3,      MB(6) },	/* 12-way set assoc, 64 byte line size */

	{ 0x4b, LVL_3,      MB(8) },	/* 16-way set assoc, 64 byte line size */
@@ -87,6 +89,7 @@ static const struct _cache_table __cpuinitconst cache_table[] = 
	{ 0x7c, LVL_2,      MB(1) },	/* 8-way set assoc, sectored cache, 64 byte line size */

	{ 0x7d, LVL_2,      MB(2) },	/* 8-way set assoc, 64 byte line size */

	{ 0x7f, LVL_2,      512 },	/* 2-way set assoc, 64 byte line size */

	{ 0x80, LVL_2,      512 },	/* 8-way set assoc, 64 byte line size */

	{ 0x82, LVL_2,      256 },	/* 8-way set assoc, 32 byte line size */

	{ 0x83, LVL_2,      512 },	/* 8-way set assoc, 32 byte line size */

	{ 0x84, LVL_2,      MB(1) },	/* 8-way set assoc, 32 byte line size */

arch/x86/kernel/cpu/mcheck/therm_throt.c

+1 −0
Original line number Diff line number Diff line
@@ -59,6 +59,7 @@ struct thermal_state { 


/* Callback to handle core threshold interrupts */

int (*platform_thermal_notify)(__u64 msr_val);

EXPORT_SYMBOL(platform_thermal_notify);



static DEFINE_PER_CPU(struct thermal_state, thermal_state);