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Commit 437541e7 authored by Rajan Vaja's avatar Rajan Vaja Committed by Michal Simek
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dt-bindings: xilinx: Separate clock binding from firmware doc 



Clock description is part of firmware doc. Move clock description
in separate doc.

Signed-off-by: default avatarRajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: default avatarJolly Shah <jollys@xilinx.com>
Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
parent 31a2d511

Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.txt

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+63 −0
Original line number Diff line number Diff line 
--------------------------------------------------------------------------

Device Tree Clock bindings for the Zynq Ultrascale+ MPSoC controlled using

Zynq MPSoC firmware interface

--------------------------------------------------------------------------

The clock controller is a h/w block of Zynq Ultrascale+ MPSoC clock

tree. It reads required input clock frequencies from the devicetree and acts

as clock provider for all clock consumers of PS clocks.



See clock_bindings.txt for more information on the generic clock bindings.



Required properties:

 - #clock-cells:	Must be 1

 - compatible:		Must contain:	"xlnx,zynqmp-clk"

 - clocks:		List of clock specifiers which are external input

			clocks to the given clock controller. Please refer

			the next section to find the input clocks for a

			given controller.

 - clock-names:		List of clock names which are exteral input clocks

			to the given clock controller. Please refer to the

			clock bindings for more details.



Input clocks for zynqmp Ultrascale+ clock controller:



The Zynq UltraScale+ MPSoC has one primary and four alternative reference clock

inputs. These required clock inputs are:

 - pss_ref_clk (PS reference clock)

 - video_clk (reference clock for video system )

 - pss_alt_ref_clk (alternative PS reference clock)

 - aux_ref_clk

 - gt_crx_ref_clk (transceiver reference clock)



The following strings are optional parameters to the 'clock-names' property in

order to provide an optional (E)MIO clock source:

 - swdt0_ext_clk

 - swdt1_ext_clk

 - gem0_emio_clk

 - gem1_emio_clk

 - gem2_emio_clk

 - gem3_emio_clk

 - mio_clk_XX		# with XX = 00..77

 - mio_clk_50_or_51	#for the mux clock to gem tsu from 50 or 51





Output clocks are registered based on clock information received

from firmware. Output clocks indexes are mentioned in

include/dt-bindings/clock/xlnx-zynqmp-clk.h.



-------

Example

-------



firmware {

	zynqmp_firmware: zynqmp-firmware {

		compatible = "xlnx,zynqmp-firmware";

		method = "smc";

		zynqmp_clk: clock-controller {

			#clock-cells = <1>;

			compatible = "xlnx,zynqmp-clk";

			clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <&gt_crx_ref_clk>;

			clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";

		};

	};

};

Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt

+1 −53
Original line number Diff line number Diff line
@@ -17,53 +17,6 @@ Required properties: 
		  - "smc" : SMC #0, following the SMCCC

		  - "hvc" : HVC #0, following the SMCCC



--------------------------------------------------------------------------

Device Tree Clock bindings for the Zynq Ultrascale+ MPSoC controlled using

Zynq MPSoC firmware interface

--------------------------------------------------------------------------

The clock controller is a h/w block of Zynq Ultrascale+ MPSoC clock

tree. It reads required input clock frequencies from the devicetree and acts

as clock provider for all clock consumers of PS clocks.



See clock_bindings.txt for more information on the generic clock bindings.



Required properties:

 - #clock-cells:	Must be 1

 - compatible:		Must contain:	"xlnx,zynqmp-clk"

 - clocks:		List of clock specifiers which are external input

			clocks to the given clock controller. Please refer

			the next section to find the input clocks for a

			given controller.

 - clock-names:		List of clock names which are exteral input clocks

			to the given clock controller. Please refer to the

			clock bindings for more details.



Input clocks for zynqmp Ultrascale+ clock controller:



The Zynq UltraScale+ MPSoC has one primary and four alternative reference clock

inputs. These required clock inputs are:

 - pss_ref_clk (PS reference clock)

 - video_clk (reference clock for video system )

 - pss_alt_ref_clk (alternative PS reference clock)

 - aux_ref_clk

 - gt_crx_ref_clk (transceiver reference clock)



The following strings are optional parameters to the 'clock-names' property in

order to provide an optional (E)MIO clock source:

 - swdt0_ext_clk

 - swdt1_ext_clk

 - gem0_emio_clk

 - gem1_emio_clk

 - gem2_emio_clk

 - gem3_emio_clk

 - mio_clk_XX		# with XX = 00..77

 - mio_clk_50_or_51	#for the mux clock to gem tsu from 50 or 51





Output clocks are registered based on clock information received

from firmware. Output clocks indexes are mentioned in

include/dt-bindings/clock/xlnx-zynqmp-clk.h.



-------

Example

-------
@@ -72,11 +25,6 @@ firmware { 
	zynqmp_firmware: zynqmp-firmware {

		compatible = "xlnx,zynqmp-firmware";

		method = "smc";

		zynqmp_clk: clock-controller {

			#clock-cells = <1>;

			compatible = "xlnx,zynqmp-clk";

			clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <&gt_crx_ref_clk>;

			clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";

		};

		...

	};

};