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Commit 4352aa5b authored by Alexander Duyck's avatar Alexander Duyck Committed by Jesse Barnes
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PCI aerdrv: use correct bit defines and add 2ms delay to aer_root_reset 



While testing completion timeouts I found that hardware was not recovering.
It looks like the hot reset was never being propagated to the endpoint
devices on the bus due to the fact that we were clearing the bit too
quickly.

The documentation I have states that we should be transmitting hot reset
TS1s for 2ms.  To achieve this I have added a 2ms delay from the time we
set the secondary bus reset bit to the time we clear it.  In addition I
changed the define used for the secondary bus reset bit to match the
register define that was being used.

Reviewed-by: default avatarHidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
Signed-off-by: default avatarAlexander Duyck <alexander.h.duyck@intel.com>
Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
parent 73a0e614

drivers/pci/pcie/aer/aerdrv.c

+8 −2
Original line number Diff line number Diff line
@@ -244,11 +244,17 @@ static pci_ers_result_t aer_root_reset(struct pci_dev *dev) 


	/* Assert Secondary Bus Reset */

	pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &p2p_ctrl);

	p2p_ctrl |= PCI_CB_BRIDGE_CTL_CB_RESET;

	p2p_ctrl |= PCI_BRIDGE_CTL_BUS_RESET;

	pci_write_config_word(dev, PCI_BRIDGE_CONTROL, p2p_ctrl);



	/*

	 * we should send hot reset message for 2ms to allow it time to

	 * propogate to all downstream ports

	 */

	msleep(2);



	/* De-assert Secondary Bus Reset */

	p2p_ctrl &= ~PCI_CB_BRIDGE_CTL_CB_RESET;

	p2p_ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;

	pci_write_config_word(dev, PCI_BRIDGE_CONTROL, p2p_ctrl);



	/*