Merge "dt-bindings: clock: Add clock-ids for SM6150"

/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2020, The Linux Foundation. All rights reserved.

 */

#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SCSHRIKE_H

#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SCSHRIKE_H

/* CAM_CC clocks */

#define CAM_CC_PLL0						0

#define CAM_CC_PLL0_OUT_EVEN					1

#define CAM_CC_PLL0_OUT_ODD					2

#define CAM_CC_PLL1						3

#define CAM_CC_PLL2						4

#define CAM_CC_PLL2_OUT_MAIN					5

#define CAM_CC_PLL3						6

#define CAM_CC_PLL4						7

#define CAM_CC_PLL5						8

#define CAM_CC_PLL6						9

#define CAM_CC_BPS_AHB_CLK					10

#define CAM_CC_BPS_AREG_CLK					11

#define CAM_CC_BPS_AXI_CLK					12

#define CAM_CC_BPS_CLK						13

#define CAM_CC_BPS_CLK_SRC					14

#define CAM_CC_CAMNOC_AXI_CLK					15

#define CAM_CC_CAMNOC_AXI_CLK_SRC				16

#define CAM_CC_CAMNOC_DCD_XO_CLK				17

#define CAM_CC_CCI_0_CLK					18

#define CAM_CC_CCI_0_CLK_SRC					19

#define CAM_CC_CCI_1_CLK					20

#define CAM_CC_CCI_1_CLK_SRC					21

#define CAM_CC_CCI_2_CLK					22

#define CAM_CC_CCI_2_CLK_SRC					23

#define CAM_CC_CCI_3_CLK					24

#define CAM_CC_CCI_3_CLK_SRC					25

#define CAM_CC_CORE_AHB_CLK					26

#define CAM_CC_CPAS_AHB_CLK					27

#define CAM_CC_CPHY_RX_CLK_SRC					28

#define CAM_CC_CSI0PHYTIMER_CLK					29

#define CAM_CC_CSI0PHYTIMER_CLK_SRC				30

#define CAM_CC_CSI1PHYTIMER_CLK					31

#define CAM_CC_CSI1PHYTIMER_CLK_SRC				32

#define CAM_CC_CSI2PHYTIMER_CLK					33

#define CAM_CC_CSI2PHYTIMER_CLK_SRC				34

#define CAM_CC_CSI3PHYTIMER_CLK					35

#define CAM_CC_CSI3PHYTIMER_CLK_SRC				36

#define CAM_CC_CSIPHY0_CLK					37

#define CAM_CC_CSIPHY1_CLK					38

#define CAM_CC_CSIPHY2_CLK					39

#define CAM_CC_CSIPHY3_CLK					40

#define CAM_CC_FAST_AHB_CLK_SRC					41

#define CAM_CC_FD_CORE_CLK					42

#define CAM_CC_FD_CORE_CLK_SRC					43

#define CAM_CC_FD_CORE_UAR_CLK					44

#define CAM_CC_GDSC_CLK						45

#define CAM_CC_ICP_AHB_CLK					46

#define CAM_CC_ICP_CLK						47

#define CAM_CC_ICP_CLK_SRC					48

#define CAM_CC_IFE_0_AXI_CLK					49

#define CAM_CC_IFE_0_CLK					50

#define CAM_CC_IFE_0_CLK_SRC					51

#define CAM_CC_IFE_0_CPHY_RX_CLK				52

#define CAM_CC_IFE_0_CSID_CLK					53

#define CAM_CC_IFE_0_CSID_CLK_SRC				54

#define CAM_CC_IFE_0_DSP_CLK					55

#define CAM_CC_IFE_1_AXI_CLK					56

#define CAM_CC_IFE_1_CLK					57

#define CAM_CC_IFE_1_CLK_SRC					58

#define CAM_CC_IFE_1_CPHY_RX_CLK				59

#define CAM_CC_IFE_1_CSID_CLK					60

#define CAM_CC_IFE_1_CSID_CLK_SRC				61

#define CAM_CC_IFE_1_DSP_CLK					62

#define CAM_CC_IFE_2_AXI_CLK					63

#define CAM_CC_IFE_2_CLK					64

#define CAM_CC_IFE_2_CLK_SRC					65

#define CAM_CC_IFE_2_CPHY_RX_CLK				66

#define CAM_CC_IFE_2_CSID_CLK					67

#define CAM_CC_IFE_2_CSID_CLK_SRC				68

#define CAM_CC_IFE_2_DSP_CLK					69

#define CAM_CC_IFE_3_AXI_CLK					70

#define CAM_CC_IFE_3_CLK					71

#define CAM_CC_IFE_3_CLK_SRC					72

#define CAM_CC_IFE_3_CPHY_RX_CLK				73

#define CAM_CC_IFE_3_CSID_CLK					74

#define CAM_CC_IFE_3_CSID_CLK_SRC				75

#define CAM_CC_IFE_3_DSP_CLK					76

#define CAM_CC_IFE_LITE_0_CLK					77

#define CAM_CC_IFE_LITE_0_CLK_SRC				78

#define CAM_CC_IFE_LITE_0_CPHY_RX_CLK				79

#define CAM_CC_IFE_LITE_0_CSID_CLK				80

#define CAM_CC_IFE_LITE_0_CSID_CLK_SRC				81

#define CAM_CC_IFE_LITE_1_CLK					82

#define CAM_CC_IFE_LITE_1_CLK_SRC				83

#define CAM_CC_IFE_LITE_1_CPHY_RX_CLK				84

#define CAM_CC_IFE_LITE_1_CSID_CLK				85

#define CAM_CC_IFE_LITE_1_CSID_CLK_SRC				86

#define CAM_CC_IFE_LITE_2_CLK					87

#define CAM_CC_IFE_LITE_2_CLK_SRC				88

#define CAM_CC_IFE_LITE_2_CPHY_RX_CLK				89

#define CAM_CC_IFE_LITE_2_CSID_CLK				90

#define CAM_CC_IFE_LITE_2_CSID_CLK_SRC				91

#define CAM_CC_IFE_LITE_3_CLK					92

#define CAM_CC_IFE_LITE_3_CLK_SRC				93

#define CAM_CC_IFE_LITE_3_CPHY_RX_CLK				94

#define CAM_CC_IFE_LITE_3_CSID_CLK				95

#define CAM_CC_IFE_LITE_3_CSID_CLK_SRC				96

#define CAM_CC_IPE_0_AHB_CLK					97

#define CAM_CC_IPE_0_AREG_CLK					98

#define CAM_CC_IPE_0_AXI_CLK					99

#define CAM_CC_IPE_0_CLK					100

#define CAM_CC_IPE_0_CLK_SRC					101

#define CAM_CC_IPE_1_AHB_CLK					102

#define CAM_CC_IPE_1_AREG_CLK					103

#define CAM_CC_IPE_1_AXI_CLK					104

#define CAM_CC_IPE_1_CLK					105

#define CAM_CC_JPEG_CLK						106

#define CAM_CC_JPEG_CLK_SRC					107

#define CAM_CC_LRME_CLK						108

#define CAM_CC_LRME_CLK_SRC					109

#define CAM_CC_MCLK0_CLK					110

#define CAM_CC_MCLK0_CLK_SRC					111

#define CAM_CC_MCLK1_CLK					112

#define CAM_CC_MCLK1_CLK_SRC					113

#define CAM_CC_MCLK2_CLK					114

#define CAM_CC_MCLK2_CLK_SRC					115

#define CAM_CC_MCLK3_CLK					116

#define CAM_CC_MCLK3_CLK_SRC					117

#define CAM_CC_MCLK4_CLK					118

#define CAM_CC_MCLK4_CLK_SRC					119

#define CAM_CC_MCLK5_CLK					120

#define CAM_CC_MCLK5_CLK_SRC					121

#define CAM_CC_MCLK6_CLK					122

#define CAM_CC_MCLK6_CLK_SRC					123

#define CAM_CC_MCLK7_CLK					124

#define CAM_CC_MCLK7_CLK_SRC					125

#define CAM_CC_SLEEP_CLK					126

#define CAM_CC_SLEEP_CLK_SRC					127

#define CAM_CC_SLOW_AHB_CLK_SRC					128

#define CAM_CC_XO_CLK_SRC					129

#endif

/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2020, The Linux Foundation. All rights reserved.

 */

#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM6150_H

#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM6150_H

/* CAM_CC clocks */

#define CAM_CC_PLL0						0

#define CAM_CC_PLL1						1

#define CAM_CC_PLL2						2

#define CAM_CC_PLL2_OUT_AUX2					3

#define CAM_CC_PLL3						4

#define CAM_CC_BPS_AHB_CLK					5

#define CAM_CC_BPS_AREG_CLK					6

#define CAM_CC_BPS_AXI_CLK					7

#define CAM_CC_BPS_CLK						8

#define CAM_CC_BPS_CLK_SRC					9

#define CAM_CC_CAMNOC_ATB_CLK					10

#define CAM_CC_CAMNOC_AXI_CLK					11

#define CAM_CC_CCI_CLK						12

#define CAM_CC_CCI_CLK_SRC					13

#define CAM_CC_CORE_AHB_CLK					14

#define CAM_CC_CPAS_AHB_CLK					15

#define CAM_CC_CPHY_RX_CLK_SRC					16

#define CAM_CC_CSI0PHYTIMER_CLK					17

#define CAM_CC_CSI0PHYTIMER_CLK_SRC				18

#define CAM_CC_CSI1PHYTIMER_CLK					19

#define CAM_CC_CSI1PHYTIMER_CLK_SRC				20

#define CAM_CC_CSI2PHYTIMER_CLK					21

#define CAM_CC_CSI2PHYTIMER_CLK_SRC				22

#define CAM_CC_CSIPHY0_CLK					23

#define CAM_CC_CSIPHY1_CLK					24

#define CAM_CC_CSIPHY2_CLK					25

#define CAM_CC_FAST_AHB_CLK_SRC					26

#define CAM_CC_ICP_ATB_CLK					27

#define CAM_CC_ICP_CLK						28

#define CAM_CC_ICP_CLK_SRC					29

#define CAM_CC_ICP_CTI_CLK					30

#define CAM_CC_IFE_0_AXI_CLK					31

#define CAM_CC_IFE_0_CLK					32

#define CAM_CC_IFE_0_CLK_SRC					33

#define CAM_CC_IFE_0_CPHY_RX_CLK				34

#define CAM_CC_IFE_0_CSID_CLK					35

#define CAM_CC_IFE_0_CSID_CLK_SRC				36

#define CAM_CC_IFE_0_DSP_CLK					37

#define CAM_CC_IFE_1_AXI_CLK					38

#define CAM_CC_IFE_1_CLK					39

#define CAM_CC_IFE_1_CLK_SRC					40

#define CAM_CC_IFE_1_CPHY_RX_CLK				41

#define CAM_CC_IFE_1_CSID_CLK					42

#define CAM_CC_IFE_1_CSID_CLK_SRC				43

#define CAM_CC_IFE_1_DSP_CLK					44

#define CAM_CC_IFE_LITE_CLK					45

#define CAM_CC_IFE_LITE_CLK_SRC					46

#define CAM_CC_IFE_LITE_CPHY_RX_CLK				47

#define CAM_CC_IFE_LITE_CSID_CLK				48

#define CAM_CC_IFE_LITE_CSID_CLK_SRC				49

#define CAM_CC_IPE_0_AHB_CLK					50

#define CAM_CC_IPE_0_AREG_CLK					51

#define CAM_CC_IPE_0_AXI_CLK					52

#define CAM_CC_IPE_0_CLK					53

#define CAM_CC_IPE_0_CLK_SRC					54

#define CAM_CC_JPEG_CLK						55

#define CAM_CC_JPEG_CLK_SRC					56

#define CAM_CC_LRME_CLK						57

#define CAM_CC_LRME_CLK_SRC					58

#define CAM_CC_MCLK0_CLK					59

#define CAM_CC_MCLK0_CLK_SRC					60

#define CAM_CC_MCLK1_CLK					61

#define CAM_CC_MCLK1_CLK_SRC					62

#define CAM_CC_MCLK2_CLK					63

#define CAM_CC_MCLK2_CLK_SRC					64

#define CAM_CC_MCLK3_CLK					65

#define CAM_CC_MCLK3_CLK_SRC					66

#define CAM_CC_SLOW_AHB_CLK_SRC					67

#define CAM_CC_SOC_AHB_CLK					68

#define CAM_CC_SYS_TMR_CLK					69

#endif

/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2020, The Linux Foundation. All rights reserved.

 */

#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SCSHRIKE_H

#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SCSHRIKE_H

/* DISP_CC clocks */

#define DISP_CC_PLL0						0

#define DISP_CC_PLL1						1

#define DISP_CC_MDSS_AHB_CLK					2

#define DISP_CC_MDSS_AHB_CLK_SRC				3

#define DISP_CC_MDSS_BYTE0_CLK					4

#define DISP_CC_MDSS_BYTE0_CLK_SRC				5

#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC				6

#define DISP_CC_MDSS_BYTE0_INTF_CLK				7

#define DISP_CC_MDSS_BYTE1_CLK					8

#define DISP_CC_MDSS_BYTE1_CLK_SRC				9

#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC				10

#define DISP_CC_MDSS_BYTE1_INTF_CLK				11

#define DISP_CC_MDSS_DP_AUX1_CLK				12

#define DISP_CC_MDSS_DP_AUX1_CLK_SRC				13

#define DISP_CC_MDSS_DP_AUX_CLK					14

#define DISP_CC_MDSS_DP_AUX_CLK_SRC				15

#define DISP_CC_MDSS_DP_CRYPTO1_CLK				16

#define DISP_CC_MDSS_DP_CRYPTO1_CLK_SRC				17

#define DISP_CC_MDSS_DP_CRYPTO_CLK				18

#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC				19

#define DISP_CC_MDSS_DP_LINK1_CLK				20

#define DISP_CC_MDSS_DP_LINK1_CLK_SRC				21

#define DISP_CC_MDSS_DP_LINK1_INTF_CLK				22

#define DISP_CC_MDSS_DP_LINK_CLK				23

#define DISP_CC_MDSS_DP_LINK_CLK_SRC				24

#define DISP_CC_MDSS_DP_LINK_INTF_CLK				25

#define DISP_CC_MDSS_DP_PIXEL1_CLK				26

#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC				27

#define DISP_CC_MDSS_DP_PIXEL2_CLK				28

#define DISP_CC_MDSS_DP_PIXEL2_CLK_SRC				29

#define DISP_CC_MDSS_DP_PIXEL_CLK				30

#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC				31

#define DISP_CC_MDSS_EDP_AUX_CLK				32

#define DISP_CC_MDSS_EDP_AUX_CLK_SRC				33

#define DISP_CC_MDSS_EDP_GTC_CLK				34

#define DISP_CC_MDSS_EDP_GTC_CLK_SRC				35

#define DISP_CC_MDSS_EDP_LINK_CLK				36

#define DISP_CC_MDSS_EDP_LINK_CLK_SRC				37

#define DISP_CC_MDSS_EDP_LINK_INTF_CLK				38

#define DISP_CC_MDSS_EDP_PIXEL_CLK				39

#define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC				40

#define DISP_CC_MDSS_ESC0_CLK					41

#define DISP_CC_MDSS_ESC0_CLK_SRC				42

#define DISP_CC_MDSS_ESC1_CLK					43

#define DISP_CC_MDSS_ESC1_CLK_SRC				44

#define DISP_CC_MDSS_MDP_CLK					45

#define DISP_CC_MDSS_MDP_CLK_SRC				46

#define DISP_CC_MDSS_MDP_LUT_CLK				47

#define DISP_CC_MDSS_NON_GDSC_AHB_CLK				48

#define DISP_CC_MDSS_PCLK0_CLK					49

#define DISP_CC_MDSS_PCLK0_CLK_SRC				50

#define DISP_CC_MDSS_PCLK1_CLK					51

#define DISP_CC_MDSS_PCLK1_CLK_SRC				52

#define DISP_CC_MDSS_ROT_CLK					53

#define DISP_CC_MDSS_ROT_CLK_SRC				54

#define DISP_CC_MDSS_RSCC_AHB_CLK				55

#define DISP_CC_MDSS_RSCC_VSYNC_CLK				56

#define DISP_CC_MDSS_VSYNC_CLK					57

#define DISP_CC_MDSS_VSYNC_CLK_SRC				58

#define DISP_CC_SLEEP_CLK					59

#define DISP_CC_SLEEP_CLK_SRC					60

#define DISP_CC_XO_CLK						61

#define DISP_CC_XO_CLK_SRC					62

/* DISP_CC resets */

#define DISP_CC_MDSS_CORE_BCR					0

#define DISP_CC_MDSS_RSCC_BCR					1

#endif

/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2020, The Linux Foundation. All rights reserved.

 */

#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6150_H

#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6150_H

/* DISP_CC clocks */

#define DISP_CC_PLL0						0

#define DISP_CC_MDSS_AHB_CLK					1

#define DISP_CC_MDSS_AHB_CLK_SRC				2

#define DISP_CC_MDSS_BYTE0_CLK					3

#define DISP_CC_MDSS_BYTE0_CLK_SRC				4

#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC				5

#define DISP_CC_MDSS_BYTE0_INTF_CLK				6

#define DISP_CC_MDSS_DP_AUX_CLK					7

#define DISP_CC_MDSS_DP_AUX_CLK_SRC				8

#define DISP_CC_MDSS_DP_CRYPTO_CLK				9

#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC				10

#define DISP_CC_MDSS_DP_LINK_CLK				11

#define DISP_CC_MDSS_DP_LINK_CLK_SRC				12

#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC			13

#define DISP_CC_MDSS_DP_LINK_INTF_CLK				14

#define DISP_CC_MDSS_DP_PIXEL1_CLK				15

#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC				16

#define DISP_CC_MDSS_DP_PIXEL_CLK				17

#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC				18

#define DISP_CC_MDSS_ESC0_CLK					19

#define DISP_CC_MDSS_ESC0_CLK_SRC				20

#define DISP_CC_MDSS_MDP_CLK					21

#define DISP_CC_MDSS_MDP_CLK_SRC				22

#define DISP_CC_MDSS_MDP_LUT_CLK				23

#define DISP_CC_MDSS_NON_GDSC_AHB_CLK				24

#define DISP_CC_MDSS_PCLK0_CLK					25

#define DISP_CC_MDSS_PCLK0_CLK_SRC				26

#define DISP_CC_MDSS_ROT_CLK					27

#define DISP_CC_MDSS_ROT_CLK_SRC				28

#define DISP_CC_MDSS_RSCC_AHB_CLK				29

#define DISP_CC_MDSS_RSCC_VSYNC_CLK				30

#define DISP_CC_MDSS_VSYNC_CLK					31

#define DISP_CC_MDSS_VSYNC_CLK_SRC				32

#define DISP_CC_XO_CLK						33

#endif

/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2020, The Linux Foundation. All rights reserved.

 */

#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SCSHRIKE_H

#define _DT_BINDINGS_CLK_QCOM_GCC_SCSHRIKE_H

/* GCC clocks */

#define GPLL0							0

#define GPLL0_OUT_EVEN						1

#define GPLL4							2

#define GPLL7							3

#define GPLL9							4

#define GCC_AGGRE_NOC_PCIE_TBU_CLK				5

#define GCC_AGGRE_UFS_CARD_2_AXI_CLK				6

#define GCC_AGGRE_UFS_CARD_AXI_CLK				7

#define GCC_AGGRE_UFS_PHY_AXI_CLK				8

#define GCC_AGGRE_USB3_MP_AXI_CLK				9

#define GCC_AGGRE_USB3_PRIM_AXI_CLK				10

#define GCC_AGGRE_USB3_SEC_AXI_CLK				11

#define GCC_BOOT_ROM_AHB_CLK					12

#define GCC_CAMERA_AHB_CLK					13

#define GCC_CAMERA_HF_AXI_CLK					14

#define GCC_CAMERA_SF_AXI_CLK					15

#define GCC_CAMERA_XO_CLK					16

#define GCC_CFG_NOC_USB3_MP_AXI_CLK				17

#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK				18

#define GCC_CFG_NOC_USB3_SEC_AXI_CLK				19

#define GCC_CPUSS_AHB_CLK					20

#define GCC_CPUSS_AHB_CLK_SRC					21

#define GCC_CPUSS_DVM_BUS_CLK					22

#define GCC_CPUSS_GNOC_CLK					23

#define GCC_CPUSS_RBCPR_CLK					24

#define GCC_DDRSS_GPU_AXI_CLK					25

#define GCC_DISP_AHB_CLK					26

#define GCC_DISP_HF_AXI_CLK					27

#define GCC_DISP_SF_AXI_CLK					28

#define GCC_DISP_XO_CLK						29

#define GCC_EMAC_AXI_CLK					30

#define GCC_EMAC_PTP_CLK					31

#define GCC_EMAC_PTP_CLK_SRC					32

#define GCC_EMAC_RGMII_CLK					33

#define GCC_EMAC_RGMII_CLK_SRC					34

#define GCC_EMAC_SLV_AHB_CLK					35

#define GCC_GP1_CLK						36

#define GCC_GP1_CLK_SRC						37

#define GCC_GP2_CLK						38

#define GCC_GP2_CLK_SRC						39

#define GCC_GP3_CLK						40

#define GCC_GP3_CLK_SRC						41

#define GCC_GP4_CLK						42

#define GCC_GP4_CLK_SRC						43

#define GCC_GP5_CLK						44

#define GCC_GP5_CLK_SRC						45

#define GCC_GPU_CFG_AHB_CLK					46

#define GCC_GPU_GPLL0_CLK_SRC					47

#define GCC_GPU_GPLL0_DIV_CLK_SRC				48

#define GCC_GPU_IREF_CLK					49

#define GCC_GPU_MEMNOC_GFX_CLK					50

#define GCC_GPU_SNOC_DVM_GFX_CLK				51

#define GCC_NPU_AXI_CLK						52

#define GCC_NPU_CFG_AHB_CLK					53

#define GCC_NPU_GPLL0_CLK_SRC					54

#define GCC_NPU_GPLL0_DIV_CLK_SRC				55

#define GCC_PCIE0_PHY_REFGEN_CLK				56

#define GCC_PCIE1_PHY_REFGEN_CLK				57

#define GCC_PCIE2_PHY_REFGEN_CLK				58

#define GCC_PCIE3_PHY_REFGEN_CLK				59

#define GCC_PCIE_0_AUX_CLK					60

#define GCC_PCIE_0_AUX_CLK_SRC					61

#define GCC_PCIE_0_CFG_AHB_CLK					62

#define GCC_PCIE_0_CLKREF_CLK					63

#define GCC_PCIE_0_MSTR_AXI_CLK					64

#define GCC_PCIE_0_PIPE_CLK					65

#define GCC_PCIE_0_SLV_AXI_CLK					66

#define GCC_PCIE_0_SLV_Q2A_AXI_CLK				67

#define GCC_PCIE_1_AUX_CLK					68

#define GCC_PCIE_1_AUX_CLK_SRC					69

#define GCC_PCIE_1_CFG_AHB_CLK					70

#define GCC_PCIE_1_MSTR_AXI_CLK					71

#define GCC_PCIE_1_PIPE_CLK					72

#define GCC_PCIE_1_SLV_AXI_CLK					73

#define GCC_PCIE_1_SLV_Q2A_AXI_CLK				74

#define GCC_PCIE_2_AUX_CLK					75

#define GCC_PCIE_2_AUX_CLK_SRC					76

#define GCC_PCIE_2_CFG_AHB_CLK					77

#define GCC_PCIE_2_MSTR_AXI_CLK					78

#define GCC_PCIE_2_PIPE_CLK					79

#define GCC_PCIE_2_SLV_AXI_CLK					80

#define GCC_PCIE_2_SLV_Q2A_AXI_CLK				81

#define GCC_PCIE_3_AUX_CLK					82

#define GCC_PCIE_3_AUX_CLK_SRC					83

#define GCC_PCIE_3_CFG_AHB_CLK					84

#define GCC_PCIE_3_MSTR_AXI_CLK					85

#define GCC_PCIE_3_PIPE_CLK					86

#define GCC_PCIE_3_SLV_AXI_CLK					87

#define GCC_PCIE_3_SLV_Q2A_AXI_CLK				88

#define GCC_PCIE_PHY_AUX_CLK					89

#define GCC_PCIE_PHY_REFGEN_CLK_SRC				90

#define GCC_PDM2_CLK						91

#define GCC_PDM2_CLK_SRC					92

#define GCC_PDM_AHB_CLK						93

#define GCC_PDM_XO4_CLK						94

#define GCC_PRNG_AHB_CLK					95

#define GCC_QMIP_CAMERA_NRT_AHB_CLK				96

#define GCC_QMIP_CAMERA_RT_AHB_CLK				97

#define GCC_QMIP_DISP_AHB_CLK					98

#define GCC_QMIP_VIDEO_CVP_AHB_CLK				99

#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK				100

#define GCC_QSPI_1_CNOC_PERIPH_AHB_CLK				101

#define GCC_QSPI_1_CORE_CLK					102

#define GCC_QSPI_1_CORE_CLK_SRC					103

#define GCC_QSPI_CNOC_PERIPH_AHB_CLK				104

#define GCC_QSPI_CORE_CLK					105

#define GCC_QSPI_CORE_CLK_SRC					106

#define GCC_QUPV3_WRAP0_S0_CLK					107

#define GCC_QUPV3_WRAP0_S0_CLK_SRC				108

#define GCC_QUPV3_WRAP0_S1_CLK					109

#define GCC_QUPV3_WRAP0_S1_CLK_SRC				110

#define GCC_QUPV3_WRAP0_S2_CLK					111

#define GCC_QUPV3_WRAP0_S2_CLK_SRC				112

#define GCC_QUPV3_WRAP0_S3_CLK					113

#define GCC_QUPV3_WRAP0_S3_CLK_SRC				114

#define GCC_QUPV3_WRAP0_S4_CLK					115

#define GCC_QUPV3_WRAP0_S4_CLK_SRC				116

#define GCC_QUPV3_WRAP0_S5_CLK					117

#define GCC_QUPV3_WRAP0_S5_CLK_SRC				118

#define GCC_QUPV3_WRAP0_S6_CLK					119

#define GCC_QUPV3_WRAP0_S6_CLK_SRC				120

#define GCC_QUPV3_WRAP0_S7_CLK					121

#define GCC_QUPV3_WRAP0_S7_CLK_SRC				122

#define GCC_QUPV3_WRAP1_S0_CLK					123

#define GCC_QUPV3_WRAP1_S0_CLK_SRC				124

#define GCC_QUPV3_WRAP1_S1_CLK					125

#define GCC_QUPV3_WRAP1_S1_CLK_SRC				126

#define GCC_QUPV3_WRAP1_S2_CLK					127

#define GCC_QUPV3_WRAP1_S2_CLK_SRC				128

#define GCC_QUPV3_WRAP1_S3_CLK					129

#define GCC_QUPV3_WRAP1_S3_CLK_SRC				130

#define GCC_QUPV3_WRAP1_S4_CLK					131

#define GCC_QUPV3_WRAP1_S4_CLK_SRC				132

#define GCC_QUPV3_WRAP1_S5_CLK					133

#define GCC_QUPV3_WRAP1_S5_CLK_SRC				134

#define GCC_QUPV3_WRAP2_S0_CLK					135

#define GCC_QUPV3_WRAP2_S0_CLK_SRC				136

#define GCC_QUPV3_WRAP2_S1_CLK					137

#define GCC_QUPV3_WRAP2_S1_CLK_SRC				138

#define GCC_QUPV3_WRAP2_S2_CLK					139

#define GCC_QUPV3_WRAP2_S2_CLK_SRC				140

#define GCC_QUPV3_WRAP2_S3_CLK					141

#define GCC_QUPV3_WRAP2_S3_CLK_SRC				142

#define GCC_QUPV3_WRAP2_S4_CLK					143

#define GCC_QUPV3_WRAP2_S4_CLK_SRC				144

#define GCC_QUPV3_WRAP2_S5_CLK					145

#define GCC_QUPV3_WRAP2_S5_CLK_SRC				146

#define GCC_QUPV3_WRAP_0_M_AHB_CLK				147

#define GCC_QUPV3_WRAP_0_S_AHB_CLK				148

#define GCC_QUPV3_WRAP_1_M_AHB_CLK				149

#define GCC_QUPV3_WRAP_1_S_AHB_CLK				150

#define GCC_QUPV3_WRAP_2_M_AHB_CLK				151

#define GCC_QUPV3_WRAP_2_S_AHB_CLK				152

#define GCC_SDCC2_AHB_CLK					153

#define GCC_SDCC2_APPS_CLK					154

#define GCC_SDCC2_APPS_CLK_SRC					155

#define GCC_SDCC4_AHB_CLK					156

#define GCC_SDCC4_APPS_CLK					157

#define GCC_SDCC4_APPS_CLK_SRC					158

#define GCC_SYS_NOC_CPUSS_AHB_CLK				159

#define GCC_TSIF_AHB_CLK					160

#define GCC_TSIF_INACTIVITY_TIMERS_CLK				161

#define GCC_TSIF_REF_CLK					162

#define GCC_TSIF_REF_CLK_SRC					163

#define GCC_UFS_CARD_2_AHB_CLK					164

#define GCC_UFS_CARD_2_AXI_CLK					165

#define GCC_UFS_CARD_2_AXI_CLK_SRC				166

#define GCC_UFS_CARD_2_ICE_CORE_CLK				167

#define GCC_UFS_CARD_2_ICE_CORE_CLK_SRC				168

#define GCC_UFS_CARD_2_PHY_AUX_CLK				169

#define GCC_UFS_CARD_2_PHY_AUX_CLK_SRC				170

#define GCC_UFS_CARD_2_RX_SYMBOL_0_CLK				171

#define GCC_UFS_CARD_2_RX_SYMBOL_1_CLK				172

#define GCC_UFS_CARD_2_TX_SYMBOL_0_CLK				173

#define GCC_UFS_CARD_2_UNIPRO_CORE_CLK				174

#define GCC_UFS_CARD_2_UNIPRO_CORE_CLK_SRC			175

#define GCC_UFS_CARD_AHB_CLK					176

#define GCC_UFS_CARD_AXI_CLK					177

#define GCC_UFS_CARD_AXI_CLK_SRC				178

#define GCC_UFS_CARD_CLKREF_CLK					179

#define GCC_UFS_CARD_ICE_CORE_CLK				180

#define GCC_UFS_CARD_ICE_CORE_CLK_SRC				181

#define GCC_UFS_CARD_PHY_AUX_CLK				182

#define GCC_UFS_CARD_PHY_AUX_CLK_SRC				183

#define GCC_UFS_CARD_RX_SYMBOL_0_CLK				184

#define GCC_UFS_CARD_RX_SYMBOL_1_CLK				185

#define GCC_UFS_CARD_TX_SYMBOL_0_CLK				186

#define GCC_UFS_CARD_UNIPRO_CORE_CLK				187

#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC			188

#define GCC_UFS_MEM_CLKREF_CLK					189

#define GCC_UFS_PHY_AHB_CLK					190

#define GCC_UFS_PHY_AXI_CLK					191

#define GCC_UFS_PHY_AXI_CLK_SRC					192

#define GCC_UFS_PHY_ICE_CORE_CLK				193

#define GCC_UFS_PHY_ICE_CORE_CLK_SRC				194

#define GCC_UFS_PHY_PHY_AUX_CLK					195

#define GCC_UFS_PHY_PHY_AUX_CLK_SRC				196

#define GCC_UFS_PHY_RX_SYMBOL_0_CLK				197

#define GCC_UFS_PHY_RX_SYMBOL_1_CLK				198

#define GCC_UFS_PHY_TX_SYMBOL_0_CLK				199

#define GCC_UFS_PHY_UNIPRO_CORE_CLK				200

#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				201

#define GCC_USB30_MP_MASTER_CLK					202

#define GCC_USB30_MP_MASTER_CLK_SRC				203

#define GCC_USB30_MP_MOCK_UTMI_CLK				204

#define GCC_USB30_MP_MOCK_UTMI_CLK_SRC				205

#define GCC_USB30_MP_SLEEP_CLK					206

#define GCC_USB30_PRIM_MASTER_CLK				207

#define GCC_USB30_PRIM_MASTER_CLK_SRC				208

#define GCC_USB30_PRIM_MOCK_UTMI_CLK				209

#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			210

#define GCC_USB30_PRIM_SLEEP_CLK				211

#define GCC_USB30_SEC_MASTER_CLK				212

#define GCC_USB30_SEC_MASTER_CLK_SRC				213

#define GCC_USB30_SEC_MOCK_UTMI_CLK				214

#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC				215

#define GCC_USB30_SEC_SLEEP_CLK					216

#define GCC_USB3_MP_PHY_AUX_CLK					217

#define GCC_USB3_MP_PHY_AUX_CLK_SRC				218

#define GCC_USB3_MP_PHY_COM_AUX_CLK				219

#define GCC_USB3_MP_PHY_PIPE_0_CLK				220

#define GCC_USB3_MP_PHY_PIPE_1_CLK				221

#define GCC_USB3_PRIM_CLKREF_CLK				222

#define GCC_USB3_PRIM_PHY_AUX_CLK				223

#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				224

#define GCC_USB3_PRIM_PHY_COM_AUX_CLK				225

#define GCC_USB3_PRIM_PHY_PIPE_CLK				226

#define GCC_USB3_SEC_CLKREF_CLK					227

#define GCC_USB3_SEC_PHY_AUX_CLK				228

#define GCC_USB3_SEC_PHY_AUX_CLK_SRC				229

#define GCC_USB3_SEC_PHY_COM_AUX_CLK				230

#define GCC_USB3_SEC_PHY_PIPE_CLK				231

#define GCC_VIDEO_AHB_CLK					232

#define GCC_VIDEO_AXI0_CLK					233

#define GCC_VIDEO_AXI1_CLK					234

#define GCC_VIDEO_AXIC_CLK					235

#define GCC_VIDEO_XO_CLK					236

#define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK			237

#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK			238

#define GCC_UFS_CARD_AXI_HW_CTL_CLK				239

#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK			240

#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK				241

#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK			242

#define GCC_UFS_PHY_AXI_HW_CTL_CLK				243

#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK				244

#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK				245

#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK			246

#define GCC_PCIE_1_CLKREF_CLK					247

#define GCC_PCIE_2_CLKREF_CLK					248

#define GCC_PCIE_3_CLKREF_CLK					249

#define GCC_NPU_AT_CLK						250

#define GCC_NPU_TRIG_CLK						251

/* GCC resets */

#define GCC_EMAC_BCR						0

#define GCC_GPU_BCR							1

#define GCC_MMSS_BCR						2

#define GCC_NPU_BCR							3

#define GCC_PCIE_0_BCR						4

#define GCC_PCIE_0_PHY_BCR					5

#define GCC_PCIE_1_BCR						6

#define GCC_PCIE_1_PHY_BCR					7

#define GCC_PCIE_2_BCR						8

#define GCC_PCIE_2_PHY_BCR					9

#define GCC_PCIE_3_BCR						10

#define GCC_PCIE_3_PHY_BCR					11

#define GCC_PCIE_PHY_BCR					12

#define GCC_PDM_BCR							13

#define GCC_PRNG_BCR						14

#define GCC_QSPI_1_BCR						15

#define GCC_QSPI_BCR						16

#define GCC_QUPV3_WRAPPER_0_BCR				17

#define GCC_QUPV3_WRAPPER_1_BCR				18

#define GCC_QUPV3_WRAPPER_2_BCR				19

#define GCC_QUSB2PHY_5_BCR					20

#define GCC_QUSB2PHY_MP0_BCR				21

#define GCC_QUSB2PHY_MP1_BCR				22

#define GCC_QUSB2PHY_PRIM_BCR				23

#define GCC_QUSB2PHY_SEC_BCR				24

#define GCC_USB3_PHY_PRIM_SP0_BCR			25

#define GCC_USB3_PHY_PRIM_SP1_BCR			26

#define GCC_USB3_DP_PHY_PRIM_SP0_BCR		27

#define GCC_USB3_DP_PHY_PRIM_SP1_BCR		28

#define GCC_USB3_PHY_SEC_BCR				29

#define GCC_USB3PHY_PHY_SEC_BCR				30

#define GCC_SDCC2_BCR						31

#define GCC_SDCC4_BCR						32

#define GCC_TSIF_BCR						33

#define GCC_UFS_CARD_2_BCR					34

#define GCC_UFS_CARD_BCR					35

#define GCC_UFS_PHY_BCR						36

#define GCC_USB30_MP_BCR					37

#define GCC_USB30_PRIM_BCR					38

#define GCC_USB30_SEC_BCR					39

#define GCC_USB_PHY_CFG_AHB2PHY_BCR			40

#define GCC_VIDEO_AXIC_CLK_BCR				41

#define GCC_VIDEO_AXI0_CLK_BCR				42

#define GCC_VIDEO_AXI1_CLK_BCR				43

#define GCC_USB3_UNIPHY_MP0_BCR			44

#define GCC_USB3_UNIPHY_MP1_BCR			45

#define GCC_USB3UNIPHY_PHY_MP0_BCR			46

#define GCC_USB3UNIPHY_PHY_MP1_BCR			47

#endif