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Commit 41da1f5d authored by Maarten Lankhorst's avatar Maarten Lankhorst Committed by Jani Nikula
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drm/i915: get rid of put_shared_dpll 



Now that the pll updates are staged the put_shared_dpll function
consists only of checks that are done in check_shared_dpll_state
after a modeset too.

The changes to pll->config are overwritten by
intel_shared_dpll_commit, so this entire function is a noop.

Signed-off-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent fe4c63c8

drivers/gpu/drm/i915/intel_display.c

+3 −31
Original line number Diff line number Diff line
@@ -4199,27 +4199,6 @@ static void lpt_pch_enable(struct drm_crtc *crtc) 
	lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);

}



void intel_put_shared_dpll(struct intel_crtc *crtc)

{

	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);



	if (pll == NULL)

		return;



	if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {

		WARN(1, "bad %s crtc mask\n", pll->name);

		return;

	}



	pll->config.crtc_mask &= ~(1 << crtc->pipe);

	if (pll->config.crtc_mask == 0) {

		WARN_ON(pll->on);

		WARN_ON(pll->active);

	}



	crtc->config->shared_dpll = DPLL_ID_PRIVATE;

}



struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,

						struct intel_crtc_state *crtc_state)

{
@@ -5206,13 +5185,6 @@ static void haswell_crtc_disable(struct drm_crtc *crtc) 
		intel_disable_shared_dpll(intel_crtc);

}



static void ironlake_crtc_off(struct drm_crtc *crtc)

{

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	intel_put_shared_dpll(intel_crtc);

}





static void i9xx_pfit_enable(struct intel_crtc *crtc)

{

	struct drm_device *dev = crtc->base.dev;
@@ -14770,7 +14742,7 @@ static void intel_init_display(struct drm_device *dev) 
			haswell_crtc_compute_clock;

		dev_priv->display.crtc_enable = haswell_crtc_enable;

		dev_priv->display.crtc_disable = haswell_crtc_disable;

		dev_priv->display.off = ironlake_crtc_off;

		dev_priv->display.off = i9xx_crtc_off;

		dev_priv->display.update_primary_plane =

			skylake_update_primary_plane;

	} else if (HAS_DDI(dev)) {
@@ -14781,7 +14753,7 @@ static void intel_init_display(struct drm_device *dev) 
			haswell_crtc_compute_clock;

		dev_priv->display.crtc_enable = haswell_crtc_enable;

		dev_priv->display.crtc_disable = haswell_crtc_disable;

		dev_priv->display.off = ironlake_crtc_off;

		dev_priv->display.off = i9xx_crtc_off;

		dev_priv->display.update_primary_plane =

			ironlake_update_primary_plane;

	} else if (HAS_PCH_SPLIT(dev)) {
@@ -14792,7 +14764,7 @@ static void intel_init_display(struct drm_device *dev) 
			ironlake_crtc_compute_clock;

		dev_priv->display.crtc_enable = ironlake_crtc_enable;

		dev_priv->display.crtc_disable = ironlake_crtc_disable;

		dev_priv->display.off = ironlake_crtc_off;

		dev_priv->display.off = i9xx_crtc_off;

		dev_priv->display.update_primary_plane =

			ironlake_update_primary_plane;

	} else if (IS_VALLEYVIEW(dev)) {

drivers/gpu/drm/i915/intel_drv.h

+0 −1
Original line number Diff line number Diff line
@@ -1083,7 +1083,6 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv, 
#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)

struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,

						struct intel_crtc_state *state);

void intel_put_shared_dpll(struct intel_crtc *crtc);



void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,

		      const struct dpll *dpll);