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Commit 419e202b authored by Lucas Stach's avatar Lucas Stach Committed by Shawn Guo
Browse files

ARM: dts: imx6: add Vivante GPU nodes 



This adds the device nodes for 2D, 3D and VG GPU cores.

Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: default avatarLucas Stach <l.stach@pengutronix.de>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent cfa1dd99

arch/arm/boot/dts/imx6dl.dtsi

+5 −0
Original line number Diff line number Diff line
@@ -104,6 +104,11 @@ 
		compatible = "fsl,imx-display-subsystem";

		ports = <&ipu1_di0>, <&ipu1_di1>;

	};



	gpu-subsystem {

		compatible = "fsl,imx-gpu-subsystem";

		cores = <&gpu_2d>, <&gpu_3d>;

	};

};



&gpt {

arch/arm/boot/dts/imx6q.dtsi

+15 −0
Original line number Diff line number Diff line
@@ -154,6 +154,16 @@ 
			status = "disabled";

		};



		gpu_vg: gpu@02204000 {

			compatible = "vivante,gc";

			reg = <0x02204000 0x4000>;

			interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>,

				 <&clks IMX6QDL_CLK_GPU2D_CORE>;

			clock-names = "bus", "core";

			power-domains = <&gpc 1>;

		};



		ipu2: ipu@02800000 {

			#address-cells = <1>;

			#size-cells = <0>;
@@ -226,6 +236,11 @@ 
		compatible = "fsl,imx-display-subsystem";

		ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;

	};



	gpu-subsystem {

		compatible = "fsl,imx-gpu-subsystem";

		cores = <&gpu_2d>, <&gpu_3d>, <&gpu_vg>;

	};

};



&hdmi {

arch/arm/boot/dts/imx6qdl.dtsi

+21 −0
Original line number Diff line number Diff line
@@ -139,6 +139,27 @@ 
			};

		};



		gpu_3d: gpu@00130000 {

			compatible = "vivante,gc";

			reg = <0x00130000 0x4000>;

			interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,

				 <&clks IMX6QDL_CLK_GPU3D_CORE>,

				 <&clks IMX6QDL_CLK_GPU3D_SHADER>;

			clock-names = "bus", "core", "shader";

			power-domains = <&gpc 1>;

		};



		gpu_2d: gpu@00134000 {

			compatible = "vivante,gc";

			reg = <0x00134000 0x4000>;

			interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>,

				 <&clks IMX6QDL_CLK_GPU2D_CORE>;

			clock-names = "bus", "core";

			power-domains = <&gpc 1>;

		};



		timer@00a00600 {

			compatible = "arm,cortex-a9-twd-timer";

			reg = <0x00a00600 0x20>;