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Commit 413879a1 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'riscv-for-linus-4.16-merge_window' of... 

Merge tag 'riscv-for-linus-4.16-merge_window' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux

Pull RISC-V updates from Palmer Dabbelt:
 "This contains the fixes we'd like to target for the 4.16 merge window.
  It's not as much as I was originally hoping to do but between glibc,
  the chip, and FOSDEM there just wasn't enough time to get everything
  put together. As such, this merge window is essentially just going to
  be small changes. This includes mostly cleanups:

   - A build fix failure to the audit test cases.

     RISC-V doesn't have renameat because the generic syscall ABI moved
     to renameat2 by the time of our port. The syscall audit test cases
     don't understand this, so I added a trivial fix. This went through
     mailing list review during the 4.15 merge window, but nobody has
     picked it up so I think it's best to just do this here.

   - The removal of our command-line argument processing code. The
     "mem_end" stuff was broken and the rest duplicated generic device
     tree code. The generic code was already being called.

   - Some unused/redundant code has been removed, including
     __ARCH_HAVE_MMU, current_pgdir, and the initialization of
     init_mm.pgd.

   - SUM is disabled upon taking a trap, which means that user memory is
     protected during traps taking inside copy_{to,from}_user().

   - The sptbr CSR has been renamed to satp in C code. We haven't
     changed the assembly code in order to maintain compatibility with
     binutils 2.29, which doesn't understand the new name.

  Additionally, we're adding some new features:

   - Basic ftrace support, thanks to Alan Kao!

   - Support for ZONE_DMA32.

     This is necessary for all the normal reasons, but also to deal with
     a deficiency in the Xilinx PCIe controller we're using on our
     FPGA-based systems. While the ZONE_DMA32 addition should be
     sufficient for most uses, it doesn't complete the fix for the
     Xilinx controller.

   - TLB shootdowns now only target the harts where they're necessary,
     instead of applying to all harts in the system.

  These patches have all been sitting on our linux-next branch for a
  while now. Due to time constraints this is all I feel comfortable
  submitting during the 4.16 merge window, hopefully we'll do better
  next time!"

[ Note to self: "harts" is RISC-V speak for "hardware threads".  I had
  to look that up.    - Linus ]

* tag 'riscv-for-linus-4.16-merge_window' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux:
  riscv: inline set_pgdir into its only caller
  riscv: rename sptbr to satp
  riscv: don't read back satp in paging_init
  riscv: remove the unused current_pgdir function
  riscv: add ZONE_DMA32
  RISC-V: Limit the scope of TLB shootdowns
  riscv: disable SUM in the exception handler
  riscv: remove redundant unlikely()
  riscv: remove unused __ARCH_HAVE_MMU define
  riscv/ftrace: Add basic support
  RISC-V: Remove mem_end command line processing
  RISC-V: Remove duplicate command-line parsing logic
  audit: Avoid build failures on systems without renameat
parents 0bd2afc7 4889dec6

arch/riscv/Kconfig

+10 −0
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ config RISCV 
	select GENERIC_ATOMIC64 if !64BIT || !RISCV_ISA_A

	select ARCH_WANT_OPTIONAL_GPIOLIB

	select HAVE_MEMBLOCK

	select HAVE_MEMBLOCK_NODE_MAP

	select HAVE_DMA_API_DEBUG

	select HAVE_DMA_CONTIGUOUS

	select HAVE_GENERIC_DMA_COHERENT
@@ -43,6 +44,10 @@ config MMU 
config ARCH_PHYS_ADDR_T_64BIT

	def_bool y



config ZONE_DMA32

	bool

	default y



config ARCH_DMA_ADDR_T_64BIT

	def_bool y
@@ -55,6 +60,9 @@ config PAGE_OFFSET 
config STACKTRACE_SUPPORT

	def_bool y



config TRACE_IRQFLAGS_SUPPORT

	def_bool y



config RWSEM_GENERIC_SPINLOCK

	def_bool y
@@ -107,6 +115,8 @@ config ARCH_RV64I 
	bool "RV64I"

	select CPU_SUPPORTS_64BIT_KERNEL

	select 64BIT

	select HAVE_FUNCTION_TRACER

	select HAVE_FUNCTION_GRAPH_TRACER



endchoice

arch/riscv/include/asm/Kbuild

+0 −1
Original line number Diff line number Diff line
@@ -12,7 +12,6 @@ generic-y += errno.h 
generic-y += exec.h

generic-y += fb.h

generic-y += fcntl.h

generic-y += ftrace.h

generic-y += futex.h

generic-y += hardirq.h

generic-y += hash.h

arch/riscv/include/asm/csr.h

+7 −7
Original line number Diff line number Diff line
@@ -40,15 +40,15 @@ 
#define SR_SD   _AC(0x8000000000000000, UL) /* FS/XS dirty */

#endif



/* SPTBR flags */

/* SATP flags */

#if __riscv_xlen == 32

#define SPTBR_PPN     _AC(0x003FFFFF, UL)

#define SPTBR_MODE_32 _AC(0x80000000, UL)

#define SPTBR_MODE    SPTBR_MODE_32

#define SATP_PPN     _AC(0x003FFFFF, UL)

#define SATP_MODE_32 _AC(0x80000000, UL)

#define SATP_MODE    SATP_MODE_32

#else

#define SPTBR_PPN     _AC(0x00000FFFFFFFFFFF, UL)

#define SPTBR_MODE_39 _AC(0x8000000000000000, UL)

#define SPTBR_MODE    SPTBR_MODE_39

#define SATP_PPN     _AC(0x00000FFFFFFFFFFF, UL)

#define SATP_MODE_39 _AC(0x8000000000000000, UL)

#define SATP_MODE    SATP_MODE_39

#endif



/* Interrupt Enable and Interrupt Pending flags */

arch/riscv/include/asm/ftrace.h

0 → 100644
+10 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/* Copyright (C) 2017 Andes Technology Corporation */



/*

 * The graph frame test is not possible if CONFIG_FRAME_POINTER is not enabled.

 * Check arch/riscv/kernel/mcount.S for detail.

 */

#if defined(CONFIG_FUNCTION_GRAPH_TRACER) && defined(CONFIG_FRAME_POINTER)

#define HAVE_FUNCTION_GRAPH_FP_TEST

#endif

arch/riscv/include/asm/mmu_context.h

+6 −11
Original line number Diff line number Diff line
@@ -39,16 +39,6 @@ static inline void destroy_context(struct mm_struct *mm) 
{

}



static inline pgd_t *current_pgdir(void)

{

	return pfn_to_virt(csr_read(sptbr) & SPTBR_PPN);

}



static inline void set_pgdir(pgd_t *pgd)

{

	csr_write(sptbr, virt_to_pfn(pgd) | SPTBR_MODE);

}



/*

 * When necessary, performs a deferred icache flush for the given MM context,

 * on the local CPU.  RISC-V has no direct mechanism for instruction cache
@@ -93,7 +83,12 @@ static inline void switch_mm(struct mm_struct *prev, 
		cpumask_clear_cpu(cpu, mm_cpumask(prev));

		cpumask_set_cpu(cpu, mm_cpumask(next));



		set_pgdir(next->pgd);

		/*

		 * Use the old spbtr name instead of using the current satp

		 * name to support binutils 2.29 which doesn't know about the

		 * privileged ISA 1.10 yet.

		 */

		csr_write(sptbr, virt_to_pfn(next->pgd) | SATP_MODE);

		local_flush_tlb_all();



		flush_icache_deferred(next);