Loading msm/sde/sde_hw_catalog.c +13 −0 Original line number Diff line number Diff line Loading @@ -4740,6 +4740,19 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) sde_cfg->sui_block_xin_mask = 0x1; sde_cfg->has_hdr = false; sde_cfg->has_sui_blendstage = true; } else if (IS_MONACO_TARGET(hw_rev)) { sde_cfg->has_cwb_support = false; sde_cfg->has_qsync = true; sde_cfg->perf.min_prefill_lines = 24; sde_cfg->vbif_qos_nlvl = 8; sde_cfg->ts_prefill_rev = 2; sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0; sde_cfg->delay_prg_fetch_start = true; sde_cfg->sui_ns_allowed = true; sde_cfg->sui_misr_supported = true; sde_cfg->sui_block_xin_mask = 0x1; sde_cfg->has_hdr = false; sde_cfg->has_sui_blendstage = true; } else if (IS_LAHAINA_TARGET(hw_rev)) { sde_cfg->has_demura = true; sde_cfg->demura_supported[SSPP_DMA1][0] = 0; Loading msm/sde/sde_hw_catalog.h +2 −0 Original line number Diff line number Diff line Loading @@ -46,6 +46,7 @@ #define SDE_HW_VER_650 SDE_HW_VER(6, 5, 0) /* scuba */ #define SDE_HW_VER_660 SDE_HW_VER(6, 6, 0) /* holi */ #define SDE_HW_VER_670 SDE_HW_VER(6, 7, 0) /* shima */ #define SDE_HW_VER_680 SDE_HW_VER(6, 8, 0) /* monaco */ #define SDE_HW_VER_690 SDE_HW_VER(6, 9, 0) /* blair */ #define SDE_HW_VER_700 SDE_HW_VER(7, 0, 0) /* lahaina */ #define SDE_HW_VER_720 SDE_HW_VER(7, 2, 0) /* yupik */ Loading @@ -72,6 +73,7 @@ #define IS_SCUBA_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_650) #define IS_HOLI_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_660) #define IS_SHIMA_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_670) #define IS_MONACO_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_680) #define IS_BLAIR_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_690) #define IS_LAHAINA_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_700) #define IS_YUPIK_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_720) Loading Loading
msm/sde/sde_hw_catalog.c +13 −0 Original line number Diff line number Diff line Loading @@ -4740,6 +4740,19 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) sde_cfg->sui_block_xin_mask = 0x1; sde_cfg->has_hdr = false; sde_cfg->has_sui_blendstage = true; } else if (IS_MONACO_TARGET(hw_rev)) { sde_cfg->has_cwb_support = false; sde_cfg->has_qsync = true; sde_cfg->perf.min_prefill_lines = 24; sde_cfg->vbif_qos_nlvl = 8; sde_cfg->ts_prefill_rev = 2; sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0; sde_cfg->delay_prg_fetch_start = true; sde_cfg->sui_ns_allowed = true; sde_cfg->sui_misr_supported = true; sde_cfg->sui_block_xin_mask = 0x1; sde_cfg->has_hdr = false; sde_cfg->has_sui_blendstage = true; } else if (IS_LAHAINA_TARGET(hw_rev)) { sde_cfg->has_demura = true; sde_cfg->demura_supported[SSPP_DMA1][0] = 0; Loading
msm/sde/sde_hw_catalog.h +2 −0 Original line number Diff line number Diff line Loading @@ -46,6 +46,7 @@ #define SDE_HW_VER_650 SDE_HW_VER(6, 5, 0) /* scuba */ #define SDE_HW_VER_660 SDE_HW_VER(6, 6, 0) /* holi */ #define SDE_HW_VER_670 SDE_HW_VER(6, 7, 0) /* shima */ #define SDE_HW_VER_680 SDE_HW_VER(6, 8, 0) /* monaco */ #define SDE_HW_VER_690 SDE_HW_VER(6, 9, 0) /* blair */ #define SDE_HW_VER_700 SDE_HW_VER(7, 0, 0) /* lahaina */ #define SDE_HW_VER_720 SDE_HW_VER(7, 2, 0) /* yupik */ Loading @@ -72,6 +73,7 @@ #define IS_SCUBA_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_650) #define IS_HOLI_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_660) #define IS_SHIMA_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_670) #define IS_MONACO_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_680) #define IS_BLAIR_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_690) #define IS_LAHAINA_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_700) #define IS_YUPIK_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_720) Loading