Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 40d8338d authored by Radim Krčmář's avatar Radim Krčmář Committed by Paolo Bonzini
Browse files

KVM: VMX: remove functions that enable msr intercepts 



All intercepts are enabled at the beginning, so they can only be used if
we disabled an intercept that we wanted to have enabled.
This was done for TMCCT to simplify a loop that disables all x2APIC MSR
intercepts, but just keeping TMCCT enabled yields better results.

Signed-off-by: default avatarRadim Krčmář <rkrcmar@redhat.com>
parent 83bafef1

arch/x86/kvm/vmx.c

+4 −53
Original line number Diff line number Diff line
@@ -4575,41 +4575,6 @@ static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, 
	}

}



static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,

						u32 msr, int type)

{

	int f = sizeof(unsigned long);



	if (!cpu_has_vmx_msr_bitmap())

		return;



	/*

	 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals

	 * have the write-low and read-high bitmap offsets the wrong way round.

	 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.

	 */

	if (msr <= 0x1fff) {

		if (type & MSR_TYPE_R)

			/* read-low */

			__set_bit(msr, msr_bitmap + 0x000 / f);



		if (type & MSR_TYPE_W)

			/* write-low */

			__set_bit(msr, msr_bitmap + 0x800 / f);



	} else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {

		msr &= 0x1fff;

		if (type & MSR_TYPE_R)

			/* read-high */

			__set_bit(msr, msr_bitmap + 0x400 / f);



		if (type & MSR_TYPE_W)

			/* write-high */

			__set_bit(msr, msr_bitmap + 0xc00 / f);



	}

}



/*

 * If a msr is allowed by L0, we should check whether it is allowed by L1.

 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
@@ -4665,21 +4630,6 @@ static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only) 
						msr, MSR_TYPE_R | MSR_TYPE_W);

}



static void vmx_enable_intercept_msr_read_x2apic(u32 msr, bool apicv_active)

{

	if (apicv_active) {

		__vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv,

				msr, MSR_TYPE_R);

		__vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv,

				msr, MSR_TYPE_R);

	} else {

		__vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,

				msr, MSR_TYPE_R);

		__vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,

				msr, MSR_TYPE_R);

	}

}



static void vmx_disable_intercept_msr_read_x2apic(u32 msr, bool apicv_active)

{

	if (apicv_active) {
@@ -6490,11 +6440,12 @@ static __init int hardware_setup(void) 
	/*

	 * enable_apicv && kvm_vcpu_apicv_active()

	 */

	for (msr = 0x800; msr <= 0x8ff; msr++)

	for (msr = 0x800; msr <= 0x8ff; msr++) {

		if (msr == 0x839 /* TMCCT */)

			continue;

		vmx_disable_intercept_msr_read_x2apic(msr, true);

	}



	/* TMCCT */

	vmx_enable_intercept_msr_read_x2apic(0x839, true);

	/* TPR */

	vmx_disable_intercept_msr_write_x2apic(0x808, true);

	/* EOI */