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Commit 40588ca6 authored by Alexander Duyck's avatar Alexander Duyck Committed by Jeff Kirsher
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i40e/i40evf: Only track one ITR setting per ring instead of Tx/Rx



The rings are already split out into Tx and Rx rings so it doesn't make
sense to have any single ring store both a Tx and Rx itr_setting value.
Since that is the case drop the pair in favor of storing just a single ITR
value.

Signed-off-by: default avatarAlexander Duyck <alexander.h.duyck@intel.com>
Tested-by: default avatarAndrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent 11a350c9
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+6 −6
Original line number Diff line number Diff line
@@ -315,9 +315,9 @@ static void i40e_dbg_dump_vsi_seid(struct i40e_pf *pf, int seid)
			 i, rx_ring->vsi,
			 rx_ring->q_vector);
		dev_info(&pf->pdev->dev,
			 "    rx_rings[%i]: rx_itr_setting = %d (%s)\n",
			 i, rx_ring->rx_itr_setting,
			 ITR_IS_DYNAMIC(rx_ring->rx_itr_setting) ? "dynamic" : "fixed");
			 "    rx_rings[%i]: itr_setting = %d (%s)\n",
			 i, rx_ring->itr_setting,
			 ITR_IS_DYNAMIC(rx_ring->itr_setting) ? "dynamic" : "fixed");
	}
	for (i = 0; i < vsi->num_queue_pairs; i++) {
		struct i40e_ring *tx_ring = READ_ONCE(vsi->tx_rings[i]);
@@ -366,9 +366,9 @@ static void i40e_dbg_dump_vsi_seid(struct i40e_pf *pf, int seid)
			 "    tx_rings[%i]: DCB tc = %d\n",
			 i, tx_ring->dcb_tc);
		dev_info(&pf->pdev->dev,
			 "    tx_rings[%i]: tx_itr_setting = %d (%s)\n",
			 i, tx_ring->tx_itr_setting,
			 ITR_IS_DYNAMIC(tx_ring->tx_itr_setting) ? "dynamic" : "fixed");
			 "    tx_rings[%i]: itr_setting = %d (%s)\n",
			 i, tx_ring->itr_setting,
			 ITR_IS_DYNAMIC(tx_ring->itr_setting) ? "dynamic" : "fixed");
	}
	rcu_read_unlock();
	dev_info(&pf->pdev->dev,
+16 −16
Original line number Diff line number Diff line
@@ -2244,14 +2244,14 @@ static int __i40e_get_coalesce(struct net_device *netdev,
	rx_ring = vsi->rx_rings[queue];
	tx_ring = vsi->tx_rings[queue];

	if (ITR_IS_DYNAMIC(rx_ring->rx_itr_setting))
	if (ITR_IS_DYNAMIC(rx_ring->itr_setting))
		ec->use_adaptive_rx_coalesce = 1;

	if (ITR_IS_DYNAMIC(tx_ring->tx_itr_setting))
	if (ITR_IS_DYNAMIC(tx_ring->itr_setting))
		ec->use_adaptive_tx_coalesce = 1;

	ec->rx_coalesce_usecs = rx_ring->rx_itr_setting & ~I40E_ITR_DYNAMIC;
	ec->tx_coalesce_usecs = tx_ring->tx_itr_setting & ~I40E_ITR_DYNAMIC;
	ec->rx_coalesce_usecs = rx_ring->itr_setting & ~I40E_ITR_DYNAMIC;
	ec->tx_coalesce_usecs = tx_ring->itr_setting & ~I40E_ITR_DYNAMIC;

	/* we use the _usecs_high to store/set the interrupt rate limit
	 * that the hardware supports, that almost but not quite
@@ -2315,26 +2315,26 @@ static void i40e_set_itr_per_queue(struct i40e_vsi *vsi,

	intrl = i40e_intrl_usec_to_reg(vsi->int_rate_limit);

	rx_ring->rx_itr_setting = ec->rx_coalesce_usecs;
	tx_ring->tx_itr_setting = ec->tx_coalesce_usecs;
	rx_ring->itr_setting = ec->rx_coalesce_usecs;
	tx_ring->itr_setting = ec->tx_coalesce_usecs;

	if (ec->use_adaptive_rx_coalesce)
		rx_ring->rx_itr_setting |= I40E_ITR_DYNAMIC;
		rx_ring->itr_setting |= I40E_ITR_DYNAMIC;
	else
		rx_ring->rx_itr_setting &= ~I40E_ITR_DYNAMIC;
		rx_ring->itr_setting &= ~I40E_ITR_DYNAMIC;

	if (ec->use_adaptive_tx_coalesce)
		tx_ring->tx_itr_setting |= I40E_ITR_DYNAMIC;
		tx_ring->itr_setting |= I40E_ITR_DYNAMIC;
	else
		tx_ring->tx_itr_setting &= ~I40E_ITR_DYNAMIC;
		tx_ring->itr_setting &= ~I40E_ITR_DYNAMIC;

	q_vector = rx_ring->q_vector;
	q_vector->rx.itr = ITR_TO_REG(rx_ring->rx_itr_setting);
	q_vector->rx.itr = ITR_TO_REG(rx_ring->itr_setting);
	vector = vsi->base_vector + q_vector->v_idx;
	wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1), q_vector->rx.itr);

	q_vector = tx_ring->q_vector;
	q_vector->tx.itr = ITR_TO_REG(tx_ring->tx_itr_setting);
	q_vector->tx.itr = ITR_TO_REG(tx_ring->itr_setting);
	vector = vsi->base_vector + q_vector->v_idx;
	wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1), q_vector->tx.itr);

@@ -2364,11 +2364,11 @@ static int __i40e_set_coalesce(struct net_device *netdev,
		vsi->work_limit = ec->tx_max_coalesced_frames_irq;

	if (queue < 0) {
		cur_rx_itr = vsi->rx_rings[0]->rx_itr_setting;
		cur_tx_itr = vsi->tx_rings[0]->tx_itr_setting;
		cur_rx_itr = vsi->rx_rings[0]->itr_setting;
		cur_tx_itr = vsi->tx_rings[0]->itr_setting;
	} else if (queue < vsi->num_queue_pairs) {
		cur_rx_itr = vsi->rx_rings[queue]->rx_itr_setting;
		cur_tx_itr = vsi->tx_rings[queue]->tx_itr_setting;
		cur_rx_itr = vsi->rx_rings[queue]->itr_setting;
		cur_tx_itr = vsi->tx_rings[queue]->itr_setting;
	} else {
		netif_info(pf, drv, netdev, "Invalid queue value, queue range is 0 - %d\n",
			   vsi->num_queue_pairs - 1);
+7 −7
Original line number Diff line number Diff line
@@ -3450,11 +3450,11 @@ static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
		struct i40e_q_vector *q_vector = vsi->q_vectors[i];

		q_vector->itr_countdown = ITR_COUNTDOWN_START;
		q_vector->rx.itr = ITR_TO_REG(vsi->rx_rings[i]->rx_itr_setting);
		q_vector->rx.itr = ITR_TO_REG(vsi->rx_rings[i]->itr_setting);
		q_vector->rx.latency_range = I40E_LOW_LATENCY;
		wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
		     q_vector->rx.itr);
		q_vector->tx.itr = ITR_TO_REG(vsi->tx_rings[i]->tx_itr_setting);
		q_vector->tx.itr = ITR_TO_REG(vsi->tx_rings[i]->itr_setting);
		q_vector->tx.latency_range = I40E_LOW_LATENCY;
		wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
		     q_vector->tx.itr);
@@ -3559,10 +3559,10 @@ static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)

	/* set the ITR configuration */
	q_vector->itr_countdown = ITR_COUNTDOWN_START;
	q_vector->rx.itr = ITR_TO_REG(vsi->rx_rings[0]->rx_itr_setting);
	q_vector->rx.itr = ITR_TO_REG(vsi->rx_rings[0]->itr_setting);
	q_vector->rx.latency_range = I40E_LOW_LATENCY;
	wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
	q_vector->tx.itr = ITR_TO_REG(vsi->tx_rings[0]->tx_itr_setting);
	q_vector->tx.itr = ITR_TO_REG(vsi->tx_rings[0]->itr_setting);
	q_vector->tx.latency_range = I40E_LOW_LATENCY;
	wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);

@@ -10018,7 +10018,7 @@ static int i40e_alloc_rings(struct i40e_vsi *vsi)
		ring->dcb_tc = 0;
		if (vsi->back->hw_features & I40E_HW_WB_ON_ITR_CAPABLE)
			ring->flags = I40E_TXR_FLAGS_WB_ON_ITR;
		ring->tx_itr_setting = pf->tx_itr_default;
		ring->itr_setting = pf->tx_itr_default;
		vsi->tx_rings[i] = ring++;

		if (!i40e_enabled_xdp_vsi(vsi))
@@ -10036,7 +10036,7 @@ static int i40e_alloc_rings(struct i40e_vsi *vsi)
		if (vsi->back->hw_features & I40E_HW_WB_ON_ITR_CAPABLE)
			ring->flags = I40E_TXR_FLAGS_WB_ON_ITR;
		set_ring_xdp(ring);
		ring->tx_itr_setting = pf->tx_itr_default;
		ring->itr_setting = pf->tx_itr_default;
		vsi->xdp_rings[i] = ring++;

setup_rx:
@@ -10049,7 +10049,7 @@ static int i40e_alloc_rings(struct i40e_vsi *vsi)
		ring->count = vsi->num_desc;
		ring->size = 0;
		ring->dcb_tc = 0;
		ring->rx_itr_setting = pf->rx_itr_default;
		ring->itr_setting = pf->rx_itr_default;
		vsi->rx_rings[i] = ring;
	}

+3 −3
Original line number Diff line number Diff line
@@ -2290,12 +2290,12 @@ static u32 i40e_buildreg_itr(const int type, const u16 itr)
#define INTREG I40E_PFINT_DYN_CTLN
static inline int get_rx_itr(struct i40e_vsi *vsi, int idx)
{
	return vsi->rx_rings[idx]->rx_itr_setting;
	return vsi->rx_rings[idx]->itr_setting;
}

static inline int get_tx_itr(struct i40e_vsi *vsi, int idx)
{
	return vsi->tx_rings[idx]->tx_itr_setting;
	return vsi->tx_rings[idx]->itr_setting;
}

/**
@@ -2322,7 +2322,7 @@ static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
	/* avoid dynamic calculation if in countdown mode OR if
	 * all dynamic is disabled
	 */
	rxval = txval = i40e_buildreg_itr(I40E_ITR_NONE, 0);
	txval = i40e_buildreg_itr(I40E_ITR_NONE, 0);

	rx_itr_setting = get_rx_itr(vsi, idx);
	tx_itr_setting = get_tx_itr(vsi, idx);
+1 −2
Original line number Diff line number Diff line
@@ -382,8 +382,7 @@ struct i40e_ring {
	 * these values always store the USER setting, and must be converted
	 * before programming to a register.
	 */
	u16 rx_itr_setting;
	u16 tx_itr_setting;
	u16 itr_setting;

	u16 count;			/* Number of descriptors */
	u16 reg_idx;			/* HW register index of the ring */
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