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Commit 3feae784 authored by Manuel Lauss's avatar Manuel Lauss Committed by Ralf Baechle
Browse files

MIPS: Alchemy: usb: use clk framework 



Add use of the common clock framework to set and enable the 48MHz
clock source for the onchip OHCI and UDC blocks.

Tested on a DB1500.  (Au1200 and Au1300 use an external 48MHz crystal).

Signed-off-by: default avatarManuel Lauss <manuel.lauss@gmail.com>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/7467/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 5a2fb71e

arch/mips/alchemy/common/usb.c

+40 −7
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ 
 *

 */



#include <linux/clk.h>

#include <linux/init.h>

#include <linux/io.h>

#include <linux/module.h>
@@ -387,10 +388,25 @@ static inline void au1200_usb_init(void) 
	udelay(1000);

}



static inline void au1000_usb_init(unsigned long rb, int reg)

static inline int au1000_usb_init(unsigned long rb, int reg)

{

	void __iomem *base = (void __iomem *)KSEG1ADDR(rb + reg);

	unsigned long r = __raw_readl(base);

	struct clk *c;



	/* 48MHz check. Don't init if no one can provide it */

	c = clk_get(NULL, "usbh_clk");

	if (IS_ERR(c))

		return -ENODEV;

	if (clk_round_rate(c, 48000000) != 48000000) {

		clk_put(c);

		return -ENODEV;

	}

	if (clk_set_rate(c, 48000000)) {

		clk_put(c);

		return -ENODEV;

	}

	clk_put(c);



#if defined(__BIG_ENDIAN)

	r |= USBHEN_BE;
@@ -400,6 +416,8 @@ static inline void au1000_usb_init(unsigned long rb, int reg) 
	__raw_writel(r, base);

	wmb();

	udelay(1000);



	return 0;

}
@@ -407,8 +425,15 @@ static inline void __au1xx0_ohci_control(int enable, unsigned long rb, int creg) 
{

	void __iomem *base = (void __iomem *)KSEG1ADDR(rb);

	unsigned long r = __raw_readl(base + creg);

	struct clk *c = clk_get(NULL, "usbh_clk");



	if (IS_ERR(c))

		return;



	if (enable) {

		if (clk_prepare_enable(c))

			goto out;



		__raw_writel(r | USBHEN_CE, base + creg);

		wmb();

		udelay(1000);
@@ -423,7 +448,10 @@ static inline void __au1xx0_ohci_control(int enable, unsigned long rb, int creg) 
	} else {

		__raw_writel(r & ~(USBHEN_CE | USBHEN_E), base + creg);

		wmb();

		clk_disable_unprepare(c);

	}

out:

	clk_put(c);

}



static inline int au1000_usb_control(int block, int enable, unsigned long rb,
@@ -569,14 +597,18 @@ static struct syscore_ops alchemy_usb_pm_ops = { 


static int __init alchemy_usb_init(void)

{

	int ret = 0;



	switch (alchemy_get_cputype()) {

	case ALCHEMY_CPU_AU1000:

	case ALCHEMY_CPU_AU1500:

	case ALCHEMY_CPU_AU1100:

		au1000_usb_init(AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG);

		ret = au1000_usb_init(AU1000_USB_OHCI_PHYS_ADDR,

				      AU1000_OHCICFG);

		break;

	case ALCHEMY_CPU_AU1550:

		au1000_usb_init(AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG);

		ret = au1000_usb_init(AU1550_USB_OHCI_PHYS_ADDR,

				      AU1550_OHCICFG);

		break;

	case ALCHEMY_CPU_AU1200:

		au1200_usb_init();
@@ -586,8 +618,9 @@ static int __init alchemy_usb_init(void) 
		break;

	}



	if (!ret)

		register_syscore_ops(&alchemy_usb_pm_ops);



	return 0;

	return ret;

}

arch_initcall(alchemy_usb_init);