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Commit 3fe3331b authored by Kim Phillips's avatar Kim Phillips Committed by Ingo Molnar
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perf/x86/amd: Add event map for AMD Family 17h 

Family 17h differs from prior families by:

 - Does not support an L2 cache miss event
 - It has re-enumerated PMC counters for:
   - L2 cache references
   - front & back end stalled cycles

So we add a new amd_f17h_perfmon_event_map[] so that the generic
perf event names will resolve to the correct h/w events on
family 17h and above processors.

Reference sections 2.1.13.3.3 (stalls) and 2.1.13.3.6 (L2):

  https://www.amd.com/system/files/TechDocs/54945_PPR_Family_17h_Models_00h-0Fh.pdf



Signed-off-by: default avatarKim Phillips <kim.phillips@amd.com>
Cc: <stable@vger.kernel.org> # v4.9+
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Janakarajan Natarajan <Janakarajan.Natarajan@amd.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Martin Liška <mliska@suse.cz>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Pu Wen <puwen@hygon.cn>
Cc: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-kernel@vger.kernel.org
Fixes: e40ed154 ("perf/x86: Add perf support for AMD family-17h processors")
[ Improved the formatting a bit. ]
Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent b24131eb

arch/x86/events/amd/core.c

+26 −9
Original line number Diff line number Diff line
@@ -117,7 +117,7 @@ static __initconst const u64 amd_hw_cache_event_ids 
};



/*

 * AMD Performance Monitor K7 and later.

 * AMD Performance Monitor K7 and later, up to and including Family 16h:

 */

static const u64 amd_perfmon_event_map[PERF_COUNT_HW_MAX] =

{
@@ -131,8 +131,25 @@ static const u64 amd_perfmon_event_map[PERF_COUNT_HW_MAX] = 
	[PERF_COUNT_HW_STALLED_CYCLES_BACKEND]	= 0x00d1, /* "Dispatch stalls" event */

};



/*

 * AMD Performance Monitor Family 17h and later:

 */

static const u64 amd_f17h_perfmon_event_map[PERF_COUNT_HW_MAX] =

{

	[PERF_COUNT_HW_CPU_CYCLES]		= 0x0076,

	[PERF_COUNT_HW_INSTRUCTIONS]		= 0x00c0,

	[PERF_COUNT_HW_CACHE_REFERENCES]	= 0xff60,

	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS]	= 0x00c2,

	[PERF_COUNT_HW_BRANCH_MISSES]		= 0x00c3,

	[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND]	= 0x0287,

	[PERF_COUNT_HW_STALLED_CYCLES_BACKEND]	= 0x0187,

};



static u64 amd_pmu_event_map(int hw_event)

{

	if (boot_cpu_data.x86 >= 0x17)

		return amd_f17h_perfmon_event_map[hw_event];



	return amd_perfmon_event_map[hw_event];

}