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Commit 3fc08b61 authored by Monk Liu's avatar Monk Liu Committed by Alex Deucher
Browse files

drm/amdgpu/gfx9: programing wptr_poll_addr register 



Required for SR-IOV.

Signed-off-by: default avatarMonk Liu <Monk.Liu@amd.com>
Signed-off-by: default avatarXiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ca2f1cca

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+5 −1
Original line number Diff line number Diff line
@@ -1502,7 +1502,7 @@ static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev) 
	struct amdgpu_ring *ring;

	u32 tmp;

	u32 rb_bufsz;

	u64 rb_addr, rptr_addr;

	u64 rb_addr, rptr_addr, wptr_gpu_addr;



	/* Set the write pointer delay */

	WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_DELAY), 0);
@@ -1530,6 +1530,10 @@ static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev) 
	WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_RPTR_ADDR), lower_32_bits(rptr_addr));

	WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_RPTR_ADDR_HI), upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);



	wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);

	WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO), lower_32_bits(wptr_gpu_addr));

	WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI), upper_32_bits(wptr_gpu_addr));



	mdelay(1);

	WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_CNTL), tmp);