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Commit 3f9c4dc6 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2019-07-05-1' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "I skipped last week because there wasn't much worth doing, this week
  got a few more fixes in.

  amdgpu:
   - default register value change
   - runpm regression fix
   - fan control fix

  i915:
   - fix Ironlake regression

  panfrost:
   - fix a double free

  virtio:
   - fix a locking bug

  imx:
   - crtc disable fixes"

* tag 'drm-fixes-2019-07-05-1' of git://anongit.freedesktop.org/drm/drm:
  drm/imx: only send event on crtc disable if kept disabled
  drm/imx: notify drm core before sending event during crtc disable
  drm/i915/ringbuffer: EMIT_INVALIDATE *before* switch context
  drm/amdgpu/gfx9: use reset default for PA_SC_FIFO_SIZE
  drm/amdgpu: Don't skip display settings in hwmgr_resume()
  drm/amd/powerplay: use hardware fan control if no powerplay fan table
  drm/panfrost: Fix a double-free error
  drm/etnaviv: add missing failure path to destroy suballoc
  drm/virtio: move drm_connector_update_edid_property() call
parents ee39d46d a0b2cf79

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+0 −19
Original line number Diff line number Diff line
@@ -1959,25 +1959,6 @@ static void gfx_v9_0_constants_init(struct amdgpu_device *adev) 
	mutex_unlock(&adev->srbm_mutex);



	gfx_v9_0_init_compute_vmid(adev);



	mutex_lock(&adev->grbm_idx_mutex);

	/*

	 * making sure that the following register writes will be broadcasted

	 * to all the shaders

	 */

	gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);



	WREG32_SOC15(GC, 0, mmPA_SC_FIFO_SIZE,

		   (adev->gfx.config.sc_prim_fifo_size_frontend <<

			PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |

		   (adev->gfx.config.sc_prim_fifo_size_backend <<

			PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |

		   (adev->gfx.config.sc_hiz_tile_fifo_size <<

			PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |

		   (adev->gfx.config.sc_earlyz_tile_fifo_size <<

			PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));

	mutex_unlock(&adev->grbm_idx_mutex);



}



static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)

drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c

+1 −1
Original line number Diff line number Diff line
@@ -326,7 +326,7 @@ int hwmgr_resume(struct pp_hwmgr *hwmgr) 
	if (ret)

		return ret;



	ret = psm_adjust_power_state_dynamic(hwmgr, true, NULL);

	ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);



	return ret;

}

drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c

+3 −1
Original line number Diff line number Diff line
@@ -916,8 +916,10 @@ static int init_thermal_controller( 
			PHM_PlatformCaps_ThermalController

		  );



	if (0 == powerplay_table->usFanTableOffset)

	if (0 == powerplay_table->usFanTableOffset) {

		hwmgr->thermal_controller.use_hw_fan_control = 1;

		return 0;

	}



	fan_table = (const PPTable_Generic_SubTable_Header *)

		(((unsigned long)powerplay_table) +

drivers/gpu/drm/amd/powerplay/inc/hwmgr.h

+1 −0
Original line number Diff line number Diff line
@@ -694,6 +694,7 @@ struct pp_thermal_controller_info { 
	uint8_t ucType;

	uint8_t ucI2cLine;

	uint8_t ucI2cAddress;

	uint8_t use_hw_fan_control;

	struct pp_fan_info fanInfo;

	struct pp_advance_fan_control_parameters advanceFanControlParameters;

};

drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c

+4 −0
Original line number Diff line number Diff line
@@ -2092,6 +2092,10 @@ static int polaris10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) 
		return 0;

	}



	/* use hardware fan control */

	if (hwmgr->thermal_controller.use_hw_fan_control)

		return 0;



	tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.

			usPWMMin * duty100;

	do_div(tmp64, 10000);