Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 3f9968c7 authored by Saurabh Sahu's avatar Saurabh Sahu
Browse files

ARM: dts: msm: Add GPUCC clock node and GDSCs for MONACO 

GPUCC clock nodes is required for clocks client to request,
so add support for the same. Also add the GDSCs
required by clients for MONACO.

Change-Id: I2eb3f35e48a1f7f44c93df64384cee1af871416a
parent da8ec358

qcom/monaco-gdsc.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -71,7 +71,7 @@ 
	};



	gpu_cx_gdsc: qcom,gdsc@5994064 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0x5994064 0x4>;

		regulator-name = "gpu_cx_gdsc";

		hw-ctl-addr = <&gpu_cx_hw_ctrl>;
@@ -80,7 +80,7 @@ 
	};



	gpu_gx_gdsc: qcom,gdsc@599400c {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0x599400c 0x4>;

		regulator-name = "gpu_gx_gdsc";

		sw-reset = <&gpu_gx_sw_reset>;

qcom/monaco.dtsi

+8 −3
Original line number Diff line number Diff line
@@ -710,9 +710,14 @@ 
		#reset-cells = <1>;

	};



	gpucc: clock-controller@5994000 {

		compatible = "qcom,dummycc";

		clock-output-names = "gpucc_clocks";

	gpucc: clock-controller@5990000 {

		compatible = "qcom,monaco-gpucc", "syscon";

		reg = <0x5990000 0x9000>;

		reg-names = "cc_base";

		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,

			 <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&gcc GPLL0>;

		clock-names = "bi_tcxo", "bi_tcxo_ao", "gpll0_out_main";

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};