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Commit 3f4f220f authored by Stanley Chu's avatar Stanley Chu
Browse files

UPSTREAM: scsi: ufs: ufs-mediatek: add waiting time for reference clock 

Some delays may be required either after gating or before ungating
reference clock for device according to vendor requirements.

Note that in UFS 3.0, the delay time after gating reference
clock can be defined by attribute bRefClkGatingWaitTime. Use the
formal value instead if it can be queried from device.

Bug: 151050916
(cherry picked from commit b3222c326c965f94b2e8e8ac73dc395ca82cd088)
Link: https://lore.kernel.org/r/20200220134848.8807-2-stanley.chu@mediatek.com


Reviewed-by: default avatarBean Huo <beanhuo@micron.com>
Signed-off-by: default avatarStanley Chu <stanley.chu@mediatek.com>
Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
Change-Id: I4e5deff2d358ed62bd8a884eb0d186e5651582eb
parent 71d7a866

drivers/scsi/ufs/ufs-mediatek.c

+44 −2
Original line number Diff line number Diff line
@@ -100,6 +100,17 @@ static int ufs_mtk_bind_mphy(struct ufs_hba *hba) 
	return err;

}



static void ufs_mtk_udelay(unsigned long us)

{

	if (!us)

		return;



	if (us < 10)

		udelay(us);

	else

		usleep_range(us, us + 10);

}



static int ufs_mtk_setup_ref_clk(struct ufs_hba *hba, bool on)

{

	struct ufs_mtk_host *host = ufshcd_get_variant(hba);
@@ -112,6 +123,7 @@ static int ufs_mtk_setup_ref_clk(struct ufs_hba *hba, bool on) 


	if (on) {

		ufs_mtk_ref_clk_notify(on, res);

		ufs_mtk_udelay(host->ref_clk_ungating_wait_us);

		ufshcd_writel(hba, REFCLK_REQUEST, REG_UFS_REFCLK_CTRL);

	} else {

		ufshcd_writel(hba, REFCLK_RELEASE, REG_UFS_REFCLK_CTRL);
@@ -137,12 +149,29 @@ static int ufs_mtk_setup_ref_clk(struct ufs_hba *hba, bool on) 


out:

	host->ref_clk_enabled = on;

	if (!on)

	if (!on) {

		ufs_mtk_udelay(host->ref_clk_gating_wait_us);

		ufs_mtk_ref_clk_notify(on, res);

	}



	return 0;

}



static void ufs_mtk_setup_ref_clk_wait_us(struct ufs_hba *hba,

					  u16 gating_us, u16 ungating_us)

{

	struct ufs_mtk_host *host = ufshcd_get_variant(hba);



	if (hba->dev_info.clk_gating_wait_us) {

		host->ref_clk_gating_wait_us =

			hba->dev_info.clk_gating_wait_us;

	} else {

		host->ref_clk_gating_wait_us = gating_us;

	}



	host->ref_clk_ungating_wait_us = ungating_us;

}



static u32 ufs_mtk_link_get_state(struct ufs_hba *hba)

{

	u32 val;
@@ -502,10 +531,23 @@ static void ufs_mtk_dbg_register_dump(struct ufs_hba *hba) 
static int ufs_mtk_apply_dev_quirks(struct ufs_hba *hba)

{

	struct ufs_dev_info *dev_info = &hba->dev_info;

	u16 mid = dev_info->wmanufacturerid;



	if (dev_info->wmanufacturerid == UFS_VENDOR_SAMSUNG)

	if (mid == UFS_VENDOR_SAMSUNG)

		ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 6);



	/*

	 * Decide waiting time before gating reference clock and

	 * after ungating reference clock according to vendors'

	 * requirements.

	 */

	if (mid == UFS_VENDOR_SAMSUNG)

		ufs_mtk_setup_ref_clk_wait_us(hba, 1, 1);

	else if (mid == UFS_VENDOR_SKHYNIX)

		ufs_mtk_setup_ref_clk_wait_us(hba, 30, 30);

	else if (mid == UFS_VENDOR_TOSHIBA)

		ufs_mtk_setup_ref_clk_wait_us(hba, 100, 32);



	return 0;

}

drivers/scsi/ufs/ufs-mediatek.h

+2 −0
Original line number Diff line number Diff line
@@ -92,6 +92,8 @@ struct ufs_mtk_host { 
	struct ufs_hba *hba;

	struct phy *mphy;

	bool ref_clk_enabled;

	u16 ref_clk_ungating_wait_us;

	u16 ref_clk_gating_wait_us;

};



#endif /* !_UFS_MEDIATEK_H */