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Commit 3f069622 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mtd/for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux 

Pull MTD updates from Miquel Raynal:
 "This contains the following changes for MTD:

  MTD core changes:
   - New Hyperbus framework
   - New _is_locked (concat) implementation
   - Various cleanups

  NAND core changes:
   - use longest matching pattern in ->exec_op() default parser
   - export NAND operation tracer
   - add flag to indicate panic_write in MTD
   - use kzalloc() instead of kmalloc() and memset()

  Raw NAND controller drivers changes:
   - brcmnand:
       - fix BCH ECC layout for large page NAND parts
       - fallback to detected ecc-strength, ecc-step-size
       - when oops in progress use pio and interrupt polling
       - code refactor code to introduce helper functions
       - add support for v7.3 controller
   - FSMC:
       - use nand_op_trace for operation tracing
   - GPMI:
       - move all driver code into single file
       - various cleanups (including dmaengine changes)
       - use runtime PM to manage clocks
       - implement exec_op
   - MTK:
       - correct low level time calculation of r/w cycle
       - improve data sampling timing for read cycle
       - add validity check for CE# pin setting
       - fix wrongly assigned OOB buffer pointer issue
       - re-license MTK NAND driver as Dual MIT/GPL
   - STM32:
       - manage the get_irq error case
       - increase DMA completion timeouts

  Raw NAND chips drivers changes:
   - Macronix: add read-retry support

  Onenand driver changes:
   - add support for 8Gb datasize chips
   - avoid fall-through warnings

  SPI-NAND changes:
   - define macros for page-read ops with three-byte addresses
   - add support for two-byte device IDs and then for GigaDevice
     GD5F1GQ4UFxxG
   - add initial support for Paragon PN26G0xA
   - handle the case where the last page read has bitflips

  SPI-NOR core changes:
   - add support for the mt25ql02g and w25q16jv flashes
   - print error in case of jedec read id fails
   - is25lp256: add post BFPT fix to correct the addr_width

  SPI NOR controller drivers changes:
   - intel-spi: Add support for Intel Elkhart Lake SPI serial flash
   - smt32: remove the driver as the driver was replaced by spi-stm32-qspi.c
   - cadence-quadspi: add reset control"

* tag 'mtd/for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (60 commits)
  mtd: concat: implement _is_locked mtd operation
  mtd: concat: refactor concat_lock/concat_unlock
  mtd: abi: do not use C++ style comments in uapi header
  mtd: afs: remove unneeded NULL check
  mtd: rawnand: stm32_fmc2: increase DMA completion timeouts
  mtd: rawnand: Use kzalloc() instead of kmalloc() and memset()
  mtd: hyperbus: Add driver for TI's HyperBus memory controller
  mtd: spinand: read returns badly if the last page has bitflips
  mtd: spinand: Add initial support for Paragon PN26G0xA
  mtd: rawnand: mtk: Re-license MTK NAND driver as Dual MIT/GPL
  mtd: rawnand: gpmi: remove double assignment to block_size
  dt-bindings: mtd: brcmnand: Add brcmnand, brcmnand-v7.3 support
  mtd: rawnand: brcmnand: Add support for v7.3 controller
  mtd: rawnand: brcmnand: Refactored code to introduce helper functions
  mtd: rawnand: brcmnand: When oops in progress use pio and interrupt polling
  mtd: Add flag to indicate panic_write
  mtd: rawnand: Add Macronix NAND read retry support
  mtd: onenand: Avoid fall-through warnings
  mtd: spinand: Add support for GigaDevice GD5F1GQ4UFxxG
  mtd: spinand: Add support for two-byte device IDs
  ...
parents 22608405 46ce10df

Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt

+3 −2
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ Required properties: 
                         brcm,brcmnand-v7.0

                         brcm,brcmnand-v7.1

                         brcm,brcmnand-v7.2

                         brcm,brcmnand-v7.3

                         brcm,brcmnand

- reg              : the register start and length for NAND register region.

                     (optional) Flash DMA register range (if present)
@@ -101,10 +102,10 @@ Required properties: 
                              number (e.g., 0, 1, 2, etc.)

- #address-cells            : see partition.txt

- #size-cells               : see partition.txt

- nand-ecc-strength         : see nand-controller.yaml

- nand-ecc-step-size        : must be 512 or 1024. See nand-controller.yaml



Optional properties:

- nand-ecc-strength         : see nand-controller.yaml

- nand-ecc-step-size        : must be 512 or 1024. See nand-controller.yaml

- nand-on-flash-bbt         : boolean, to enable the on-flash BBT for this

                              chip-select. See nand-controller.yaml

- brcm,nand-oob-sector-size : integer, to denote the spare area sector size

Documentation/devicetree/bindings/mtd/cadence-quadspi.txt

+5 −0
Original line number Diff line number Diff line
@@ -35,6 +35,9 @@ custom properties: 
		  (qspi_n_ss_out).

- cdns,tslch-ns : Delay in nanoseconds between setting qspi_n_ss_out low

                  and first bit transfer.

- resets	: Must contain an entry for each entry in reset-names.

		  See ../reset/reset.txt for details.

- reset-names	: Must include either "qspi" and/or "qspi-ocp".



Example:
@@ -50,6 +53,8 @@ Example: 
		cdns,fifo-depth = <128>;

		cdns,fifo-width = <4>;

		cdns,trigger-address = <0x00000000>;

		resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>;

		reset-names = "qspi", "qspi-ocp";



		flash0: n25q00@0 {

			...

Documentation/devicetree/bindings/mtd/cypress,hyperflash.txt

0 → 100644
+13 −0
Original line number Diff line number Diff line 
Bindings for HyperFlash NOR flash chips compliant with Cypress HyperBus

specification and supports Cypress CFI specification 1.5 command set.



Required properties:

- compatible : "cypress,hyperflash", "cfi-flash" for HyperFlash NOR chips

- reg : Address of flash's memory map



Example:



	flash@0 {

		compatible = "cypress,hyperflash", "cfi-flash";

		reg = <0x0 0x4000000>;

	};

Documentation/devicetree/bindings/mtd/stm32-quadspi.txt

deleted100644 → 0
+0 −43
Original line number Diff line number Diff line 
* STMicroelectronics Quad Serial Peripheral Interface(QuadSPI)



Required properties:

- compatible: should be "st,stm32f469-qspi"

- reg: the first contains the register location and length.

       the second contains the memory mapping address and length

- reg-names: should contain the reg names "qspi" "qspi_mm"

- interrupts: should contain the interrupt for the device

- clocks: the phandle of the clock needed by the QSPI controller

- A pinctrl must be defined to set pins in mode of operation for QSPI transfer



Optional properties:

- resets: must contain the phandle to the reset controller.



A spi flash must be a child of the nor_flash node and could have some

properties. Also see jedec,spi-nor.txt.



Required properties:

- reg: chip-Select number (QSPI controller may connect 2 nor flashes)

- spi-max-frequency: max frequency of spi bus



Optional property:

- spi-rx-bus-width: see ../spi/spi-bus.txt for the description



Example:



qspi: spi@a0001000 {

	compatible = "st,stm32f469-qspi";

	reg = <0xa0001000 0x1000>, <0x90000000 0x10000000>;

	reg-names = "qspi", "qspi_mm";

	interrupts = <91>;

	resets = <&rcc STM32F4_AHB3_RESET(QSPI)>;

	clocks = <&rcc 0 STM32F4_AHB3_CLOCK(QSPI)>;

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_qspi0>;



	flash@0 {

		reg = <0>;

		spi-rx-bus-width = <4>;

		spi-max-frequency = <108000000>;

		...

	};

};

Documentation/devicetree/bindings/mtd/ti,am654-hbmc.txt

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+51 −0
Original line number Diff line number Diff line 
Bindings for HyperBus Memory Controller (HBMC) on TI's K3 family of SoCs



Required properties:

- compatible : "ti,am654-hbmc" for AM654 SoC

- reg : Two entries:

	First entry pointed to the register space of HBMC controller

	Second entry pointing to the memory map region dedicated for

	MMIO access to attached flash devices

- ranges : Address translation from offset within CS to allocated MMIO

	   space in SoC



Optional properties:

- mux-controls : phandle to the multiplexer that controls selection of

		 HBMC vs OSPI inside Flash SubSystem (FSS). Default is OSPI,

		 if property is absent.

		 See Documentation/devicetree/bindings/mux/reg-mux.txt

		 for mmio-mux binding details



Example:



	system-controller@47000000 {

		compatible = "syscon", "simple-mfd";

		reg = <0x0 0x47000000 0x0 0x100>;

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;



		hbmc_mux: multiplexer {

			compatible = "mmio-mux";

			#mux-control-cells = <1>;

			mux-reg-masks = <0x4 0x2>; /* 0: reg 0x4, bit 1 */

		};

	};



	hbmc: hyperbus@47034000 {

		compatible = "ti,am654-hbmc";

		reg = <0x0 0x47034000 0x0 0x100>,

			<0x5 0x00000000 0x1 0x0000000>;

		power-domains = <&k3_pds 55>;

		#address-cells = <2>;

		#size-cells = <1>;

		ranges = <0x0 0x0 0x5 0x00000000 0x4000000>, /* CS0 - 64MB */

			 <0x1 0x0 0x5 0x04000000 0x4000000>; /* CS1 - 64MB */

		mux-controls = <&hbmc_mux 0>;



		/* Slave flash node */

		flash@0,0 {

			compatible = "cypress,hyperflash", "cfi-flash";

			reg = <0x0 0x0 0x4000000>;

		};

	};