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Commit 3ed06de5 authored by Jagadeesh Kona's avatar Jagadeesh Kona
Browse files

ARM: dts: msm: Update clock nodes and GDSC for SHIMA 

Update clock nodes of CAMCC, DEBUGCC, GPUCC, VIDEOCC,
sleep_clk and GDSC's of CAMCC, GPUCC and VIDEOCC.

Change-Id: Ic45633e064cd4c81ea6fc9336a9d9512e82dde7c
parent 3f4f4ec2

qcom/shima-gdsc.dtsi

+12 −12
Original line number Diff line number Diff line
@@ -102,42 +102,42 @@ 


	/* GDSCs in CAMCC */

	cam_cc_titan_top_gdsc: qcom,gdsc@ad0c120 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0xad0c120 0x4>;

		regulator-name = "cam_cc_titan_top_gdsc";

		status = "disabled";

	};



	cam_cc_bps_gdsc: qcom,gdsc@ad07004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0xad07004 0x4>;

		regulator-name = "cam_cc_bps_gdsc";

		status = "disabled";

	};



	cam_cc_ife_0_gdsc: qcom,gdsc@ad0a004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0xad0a004 0x4>;

		regulator-name = "cam_cc_ife_0_gdsc";

		status = "disabled";

	};



	cam_cc_ife_1_gdsc: qcom,gdsc@ad0b004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0xad0b004 0x4>;

		regulator-name = "cam_cc_ife_1_gdsc";

		status = "disabled";

	};



	cam_cc_ife_2_gdsc: qcom,gdsc@ad0b070 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0xad0b070 0x4>;

		regulator-name = "cam_cc_ife_2_gdsc";

		status = "disabled";

	};



	cam_cc_ipe_0_gdsc: qcom,gdsc@ad08004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0xad08004 0x4>;

		regulator-name = "cam_cc_ipe_0_gdsc";

		status = "disabled";
@@ -170,7 +170,7 @@ 
	};



	gpu_cx_gdsc: qcom,gdsc@3d9106c {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0x3d9106c 0x4>;

		regulator-name = "gpu_cx_gdsc";

		hw-ctrl-addr = <&gpu_cx_hw_ctrl>;
@@ -179,7 +179,7 @@ 
	};



	gpu_gx_gdsc: qcom,gdsc@3d9100c {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0x3d9100c 0x4>;

		regulator-name = "gpu_gx_gdsc";

		sw-reset = <&gpu_gx_sw_reset>;
@@ -190,28 +190,28 @@ 


	/* GDSCs in VIDEOCC */

	video_cc_mvs0_gdsc: qcom,gdsc@abf0d18 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0xabf0d18 0x4>;

		regulator-name = "video_cc_mvs0_gdsc";

		status = "disabled";

	};



	video_cc_mvs0c_gdsc: qcom,gdsc@abf0bf8 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0xabf0bf8 0x4>;

		regulator-name = "video_cc_mvs0c_gdsc";

		status = "disabled";

	};



	video_cc_mvs1_gdsc: qcom,gdsc@abf0d98 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0xabf0d98 0x4>;

		regulator-name = "video_cc_mvs1_gdsc";

		status = "disabled";

	};



	video_cc_mvs1c_gdsc: qcom,gdsc@abf0c98 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0xabf0c98 0x4>;

		regulator-name = "video_cc_mvs1c_gdsc";

		status = "disabled";

qcom/shima-rumi.dtsi

+20 −1
Original line number Diff line number Diff line 
#include <dt-bindings/clock/qcom,gcc-shima.h>



&soc {

	timer {

		clock-frequency = <5000000>;
@@ -109,5 +111,22 @@ 
};



&cpufreq_hw {

	clocks = <&bi_tcxo>, <&gcc 0>;

	clocks = <&bi_tcxo>, <&gcc GCC_GPLL0>;

};



&camcc {

	clocks = <&bi_tcxo>, <&bi_tcxo_ao>, <&sleep_clk>;

};



&debugcc {

	clocks = <&bi_tcxo>;

};



&videocc {

	clocks = <&bi_tcxo>, <&bi_tcxo_ao>, <&sleep_clk>;

};



&gpucc {

	clocks = <&bi_tcxo>, <&gcc GCC_GPU_GPLL0_CLK_SRC>,

		<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;

};

qcom/shima.dtsi

+40 −10
Original line number Diff line number Diff line
@@ -612,7 +612,7 @@ 


		sleep_clk: sleep-clk {

			compatible = "fixed-clock";

			clock-frequency = <32764>;

			clock-frequency = <32000>;

			clock-output-names = "chip_sleep_clk";

			#clock-cells = <0>;

		};
@@ -659,9 +659,15 @@ 
		#reset-cells = <1>;

	};



	camcc: qcom,camcc@ad00000 {

		compatible = "qcom,dummycc";

		clock-output-names = "camcc_clocks";

	camcc: clock-controller@ad00000 {

		compatible = "qcom,shima-camcc", "syscon";

		reg = <0xad00000 0x10000>;

		reg-names = "cc_base";

		vdd_mx-supply = <&VDD_MXA_LEVEL>;

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>,

			<&sleep_clk>;

		clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};
@@ -673,20 +679,44 @@ 
		#reset-cells = <1>;

	};



	gpucc: qcom,gpucc@3d90000 {

		compatible = "qcom,dummycc";

		clock-output-names = "gpucc_clocks";

	gpucc: clock-controller@3d90000 {

		compatible = "qcom,shima-gpucc", "syscon";

		reg = <0x3d90000 0x9000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		vdd_mx-supply = <&VDD_MXA_LEVEL>;

		clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPU_GPLL0_CLK_SRC>,

			<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;

		clock-names = "bi_tcxo", "gcc_gpu_gpll0_clk_src",

			"gcc_gpu_gpll0_div_clk_src";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	videocc: qcom,videocc@abf0000 {

		compatible = "qcom,dummycc";

		clock-output-names = "videocc_clocks";

	videocc: clock-controller@abf0000 {

		compatible = "qcom,shima-videocc", "syscon";

		reg = <0xabf0000 0x10000>;

		reg-names = "cc_base";

		vdd_mx-supply = <&VDD_MXA_LEVEL>;

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>,

			<&sleep_clk>;

		clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	debugcc: debug-clock-controller@0 {

		compatible = "qcom,shima-debugcc";

		qcom,gcc = <&gcc>;

		qcom,videocc = <&videocc>;

		qcom,camcc = <&camcc>;

		qcom,gpucc = <&gpucc>;

		clocks = <&rpmhcc RPMH_CXO_CLK>;

		clock-names = "xo_clk_src";

		#clock-cells = <1>;

	};



	cpufreq_hw: qcom,cpufreq-hw {

		compatible = "qcom,cpufreq-hw-epss";

		reg = <0x18591000 0x1000>, <0x18592000 0x1000>,