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Commit 3ecea59d authored by Aapo Vienamo's avatar Aapo Vienamo Committed by Ulf Hansson
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dt-bindings: mmc: Add DQS trim value to Tegra SDHCI 



Document HS400 DQS trim value device tree property.

Signed-off-by: default avatarAapo Vienamo <avienamo@nvidia.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Acked-by: default avatarThierry Reding <treding@nvidia.com>
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent 2ad50051

Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt

+4 −0
Original line number Diff line number Diff line
@@ -71,6 +71,7 @@ Optional properties for Tegra210 and Tegra186: 
  trimmer value for non-tunable modes.

- nvidia,default-trim : Specify the default outbound clock trimmer

  value.

- nvidia,dqs-trim : Specify DQS trim value for HS400 timing



  Notes on the pad calibration pull up and pulldown offset values:

    - The property values are drive codes which are programmed into the
@@ -87,6 +88,9 @@ Optional properties for Tegra210 and Tegra186: 
    - The values are programmed to the Vendor Clock Control Register.

      Please refer to the reference manual of the SoC for correct

      values.

    - The DQS trim values are only used on controllers which support

      HS400 timing. Only SDMMC4 on Tegra210 and Tegra 186 supports

      HS400.



Example:

sdhci@700b0000 {