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Commit 3e8a8a50 authored by Marc Zyngier's avatar Marc Zyngier
Browse files

KVM: arm: vgic-v3: Add support for ICC_SGI0R and ICC_ASGI1R accesses 



In order to generate Group0 SGIs, let's add some decoding logic to
access_gic_sgi(), and pass the generating group accordingly.

Reviewed-by: default avatarEric Auger <eric.auger@redhat.com>
Reviewed-by: default avatarChristoffer Dall <christoffer.dall@arm.com>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
parent 03bd646d

arch/arm/kvm/coproc.c

+24 −1
Original line number Diff line number Diff line
@@ -246,6 +246,7 @@ static bool access_gic_sgi(struct kvm_vcpu *vcpu, 
			   const struct coproc_reg *r)

{

	u64 reg;

	bool g1;



	if (!p->is_write)

		return read_from_write_only(vcpu, p);
@@ -253,7 +254,25 @@ static bool access_gic_sgi(struct kvm_vcpu *vcpu, 
	reg = (u64)*vcpu_reg(vcpu, p->Rt2) << 32;

	reg |= *vcpu_reg(vcpu, p->Rt1) ;



	vgic_v3_dispatch_sgi(vcpu, reg, true);

	/*

	 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R access generates

	 * Group0 SGIs only, while ICC_SGI1R can generate either group,

	 * depending on the SGI configuration. ICC_ASGI1R is effectively

	 * equivalent to ICC_SGI0R, as there is no "alternative" secure

	 * group.

	 */

	switch (p->Op1) {

	default:		/* Keep GCC quiet */

	case 0:			/* ICC_SGI1R */

		g1 = true;

		break;

	case 1:			/* ICC_ASGI1R */

	case 2:			/* ICC_SGI0R */

		g1 = false;

		break;

	}



	vgic_v3_dispatch_sgi(vcpu, reg, g1);



	return true;

}
@@ -459,6 +478,10 @@ static const struct coproc_reg cp15_regs[] = { 


	/* ICC_SGI1R */

	{ CRm64(12), Op1( 0), is64, access_gic_sgi},

	/* ICC_ASGI1R */

	{ CRm64(12), Op1( 1), is64, access_gic_sgi},

	/* ICC_SGI0R */

	{ CRm64(12), Op1( 2), is64, access_gic_sgi},



	/* VBAR: swapped by interrupt.S. */

	{ CRn(12), CRm( 0), Op1( 0), Op2( 0), is32,