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Commit 3e5d5f6b authored by Hemant Kumar's avatar Hemant Kumar
Browse files

pci: controller: msm: Poll for L0s state when disallowing L1 



If L0s link state is enabled, API to disallow L1 also needs
to poll for L0s while checking for L0. It is possible that
link goes to L0s from L0 by the time LTSSM state is checked
again.

Change-Id: Ib614860dad8c92a55f993cdb1c38bf8ebfca17a2
Signed-off-by: default avatarHemant Kumar <hemantk@codeaurora.org>
parent 653a9c02

drivers/pci/controller/pci-msm.c

+16 −3
Original line number Diff line number Diff line
@@ -2274,6 +2274,19 @@ static int msm_pcie_is_link_up(struct msm_pcie_dev_t *dev) 
			PCIE20_CAP_LINKCTRLSTATUS) & BIT(29);

}



static bool msm_pcie_check_ltssm_state(struct msm_pcie_dev_t *dev, u32 state)

{

	u32 ltssm;



	ltssm = readl_relaxed(dev->parf + PCIE20_PARF_LTSSM) &

		MSM_PCIE_LTSSM_MASK;



	if (ltssm == state)

		return true;



	return false;

}



/**

 * msm_pcie_iatu_config - configure outbound address translation region

 * @dev: root commpex
@@ -5768,9 +5781,9 @@ int msm_pcie_prevent_l1(struct pci_dev *pci_dev) 
				PCI_EXP_LNKCTL_ASPM_L1, 0);

	msm_pcie_write_mask(pcie_dev->parf + PCIE20_PARF_PM_CTRL, 0, BIT(5));



	/* confirm link is in L0 */

	while (((readl_relaxed(pcie_dev->parf + PCIE20_PARF_LTSSM) &

		MSM_PCIE_LTSSM_MASK)) != MSM_PCIE_LTSSM_L0) {

	/* confirm link is in L0/L0s */

	while (!msm_pcie_check_ltssm_state(pcie_dev, MSM_PCIE_LTSSM_L0) &&

		!msm_pcie_check_ltssm_state(pcie_dev, MSM_PCIE_LTSSM_L0S)) {

		if (unlikely(cnt++ >= cnt_max)) {

			PCIE_ERR(pcie_dev,

				"PCIe: RC%d: %02x:%02x.%01x: failed to transition to L0\n",