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Commit 3e1531db authored by Xing Zheng's avatar Xing Zheng Committed by Heiko Stuebner
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clk: rockchip: fix the incorrect pclk_edp div width for RK3399 



The range of the  pclk_edp_div_con is [13:8] and 6 bits, not 5.

Reported-by: default avatarLin Huang <hl@rock-chips.com>
Signed-off-by: default avatarXing Zheng <zhengxing@rock-chips.com>
Tested-by: default avatarLin Huang <hl@rock-chips.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 1a0abcd6

drivers/clk/rockchip/clk-rk3399.c

+1 −1
Original line number Diff line number Diff line
@@ -1132,7 +1132,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { 
			RK3399_CLKGATE_CON(11), 8, GFLAGS),



	COMPOSITE(PCLK_EDP, "pclk_edp", mux_pll_src_cpll_gpll_p, 0,

			RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 5, DFLAGS,

			RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 6, DFLAGS,

			RK3399_CLKGATE_CON(11), 11, GFLAGS),

	GATE(PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp", CLK_IGNORE_UNUSED,

			RK3399_CLKGATE_CON(32), 12, GFLAGS),