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Commit 3d920a10 authored by Linyu Yuan's avatar Linyu Yuan
Browse files

ARM: dts: msm: tune USB2 compliance for holi QRD 

Change tune1 and bias_ctrl2.

Change-Id: I1a1fa8ff315e71f7113a0c19e45e43a5a61b9b8e
parent 6749249a

qcom/holi-qrd.dtsi

+44 −0
Original line number Diff line number Diff line
@@ -400,6 +400,50 @@ 
	extcon = <&pm7250b_pdphy>, <&eud>;

};



&qusb_phy0 {

	qcom,qusb-phy-init-seq =

		/* <value reg_offset> */

		<0x23 0x210 /* PWR_CTRL1 */

		 0x03 0x04  /* PLL_ANALOG_CONTROLS_TWO */

		 0x7c 0x18c /* PLL_CLOCK_INVERTERS */

		 0x80 0x2c  /* PLL_CMODE */

		 0x0a 0x184 /* PLL_LOCK_DELAY */

		 0x19 0xb4  /* PLL_DIGITAL_TIMERS_TWO */

		 0x40 0x194 /* PLL_BIAS_CONTROL_1 */

		 0x15 0x198 /* PLL_BIAS_CONTROL_2 */

		 0x21 0x214 /* PWR_CTRL2 */

		 0x08 0x220 /* IMP_CTRL1 */

		 0x58 0x224 /* IMP_CTRL2 */

		 0x47 0x240 /* TUNE1 */

		 0x29 0x244 /* TUNE2 */

		 0xca 0x248 /* TUNE3 */

		 0x04 0x24c /* TUNE4 */

		 0x03 0x250 /* TUNE5 */

		 0x30 0x23c /* CHG_CTRL2 */

		 0x22 0x210>; /* PWR_CTRL1 */



	qcom,qusb-phy-host-init-seq =

		/* <value reg_offset> */

		<0x23 0x210 /* PWR_CTRL1 */

		0x03 0x04  /* PLL_ANALOG_CONTROLS_TWO */

		0x7c 0x18c /* PLL_CLOCK_INVERTERS */

		0x80 0x2c  /* PLL_CMODE */

		0x0a 0x184 /* PLL_LOCK_DELAY */

		0x19 0xb4  /* PLL_DIGITAL_TIMERS_TWO */

		0x40 0x194 /* PLL_BIAS_CONTROL_1 */

		0x15 0x198 /* PLL_BIAS_CONTROL_2 */

		0x21 0x214 /* PWR_CTRL2 */

		0x08 0x220 /* IMP_CTRL1 */

		0x58 0x224 /* IMP_CTRL2 */

		0x47 0x240 /* TUNE1 */

		0x29 0x244 /* TUNE2 */

		0xca 0x248 /* TUNE3 */

		0x04 0x24c /* TUNE4 */

		0x03 0x250 /* TUNE5 */

		0x30 0x23c /* CHG_CTRL2 */

		0x22 0x210>; /* PWR_CTRL1 */

};



&pm7250b_vadc {

	smb1390_therm@e {

		qcom,scale-fn-type = <ADC_SCALE_HW_CALIB_PM5_SMB1398_TEMP>;