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Commit 3d306221 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-ti-for-4.20' of... 

Merge tag 'clk-ti-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux into clk-ti

Pull TI clock driver updates from Tero Kristo:

This tag adds changes for the Texas Instruments clock driver. Included
changes are:
- clkctrl driver changes switching the layout from CM based to clockdomain
  based. Needed for ongoing hwmod transition towards sysc driver. Changed
  SoCs for this include am3,am4,am5,dra7.
- RTC+DDR sleep mode support code for clock save/restore. The deep sleep
  states will wipe the clock register space on the SoC, requiring save/
  restore support so that the state can be retained over the sleep state.

* tag 'clk-ti-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux:
  clk: ti: Add functions to save/restore clk context
  clk: clk: Add clk_gate_restore_context function
  clk: Add functions to save/restore clock context en-masse
  clk: ti: dra7: add new clkctrl data
  clk: ti: dra7xx: rename existing clkctrl data as compat data
  clk: ti: am43xx: add new clkctrl data for am43xx
  clk: ti: am43xx: rename existing clkctrl data as compat data
  clk: ti: am33xx: add new clkctrl data for am33xx
  clk: ti: am33xx: rename existing clkctrl data as compat data
  clk: ti: clkctrl: replace dashes from clkdm name with underscore
  clk: ti: clkctrl: support multiple clkctrl nodes under a cm node
  dt-bindings: clock: dra7xx: add clkctrl indices for new data layout
  dt-bindings: clock: am43xx: add clkctrl indices for new data layout
  dt-bindings: clock: am33xx: add clkctrl indices for new data layout
  clk: ti: fix OF child-node lookup
parents 5b394b2d d6e7bbc1

drivers/clk/clk.c

+93 −0
Original line number Diff line number Diff line
@@ -923,6 +923,99 @@ static int clk_core_enable_lock(struct clk_core *core) 
	return ret;

}



/**

 * clk_gate_restore_context - restore context for poweroff

 * @hw: the clk_hw pointer of clock whose state is to be restored

 *

 * The clock gate restore context function enables or disables

 * the gate clocks based on the enable_count. This is done in cases

 * where the clock context is lost and based on the enable_count

 * the clock either needs to be enabled/disabled. This

 * helps restore the state of gate clocks.

 */

void clk_gate_restore_context(struct clk_hw *hw)

{

	if (hw->clk->core->enable_count)

		hw->clk->core->ops->enable(hw);

	else

		hw->clk->core->ops->disable(hw);

}

EXPORT_SYMBOL_GPL(clk_gate_restore_context);



static int _clk_save_context(struct clk_core *clk)

{

	struct clk_core *child;

	int ret = 0;



	hlist_for_each_entry(child, &clk->children, child_node) {

		ret = _clk_save_context(child);

		if (ret < 0)

			return ret;

	}



	if (clk->ops && clk->ops->save_context)

		ret = clk->ops->save_context(clk->hw);



	return ret;

}



static void _clk_restore_context(struct clk_core *clk)

{

	struct clk_core *child;



	if (clk->ops && clk->ops->restore_context)

		clk->ops->restore_context(clk->hw);



	hlist_for_each_entry(child, &clk->children, child_node)

		_clk_restore_context(child);

}



/**

 * clk_save_context - save clock context for poweroff

 *

 * Saves the context of the clock register for powerstates in which the

 * contents of the registers will be lost. Occurs deep within the suspend

 * code.  Returns 0 on success.

 */

int clk_save_context(void)

{

	struct clk_core *clk;

	int ret;



	hlist_for_each_entry(clk, &clk_root_list, child_node) {

		ret = _clk_save_context(clk);

		if (ret < 0)

			return ret;

	}



	hlist_for_each_entry(clk, &clk_orphan_list, child_node) {

		ret = _clk_save_context(clk);

		if (ret < 0)

			return ret;

	}



	return 0;

}

EXPORT_SYMBOL_GPL(clk_save_context);



/**

 * clk_restore_context - restore clock context after poweroff

 *

 * Restore the saved clock context upon resume.

 *

 */

void clk_restore_context(void)

{

	struct clk_core *clk;



	hlist_for_each_entry(clk, &clk_root_list, child_node)

		_clk_restore_context(clk);



	hlist_for_each_entry(clk, &clk_orphan_list, child_node)

		_clk_restore_context(clk);

}

EXPORT_SYMBOL_GPL(clk_restore_context);



/**

 * clk_enable - ungate a clock

 * @clk: the clk being ungated

drivers/clk/ti/Makefile

+6 −3
Original line number Diff line number Diff line
@@ -6,7 +6,8 @@ clk-common = dpll.o composite.o divider.o gate.o \ 
					  fixed-factor.o mux.o apll.o \

					  clkt_dpll.o clkt_iclk.o clkt_dflt.o \

					  clkctrl.o

obj-$(CONFIG_SOC_AM33XX)		+= $(clk-common) clk-33xx.o dpll3xxx.o

obj-$(CONFIG_SOC_AM33XX)		+= $(clk-common) clk-33xx.o dpll3xxx.o \

					  clk-33xx-compat.o

obj-$(CONFIG_SOC_TI81XX)		+= $(clk-common) fapll.o clk-814x.o clk-816x.o

obj-$(CONFIG_ARCH_OMAP2)		+= $(clk-common) interface.o clk-2xxx.o

obj-$(CONFIG_ARCH_OMAP3)		+= $(clk-common) interface.o \
@@ -16,8 +17,10 @@ obj-$(CONFIG_ARCH_OMAP4) += $(clk-common) clk-44xx.o \ 
obj-$(CONFIG_SOC_OMAP5)			+= $(clk-common) clk-54xx.o \

					   dpll3xxx.o dpll44xx.o

obj-$(CONFIG_SOC_DRA7XX)		+= $(clk-common) clk-7xx.o \

					   clk-dra7-atl.o dpll3xxx.o dpll44xx.o

obj-$(CONFIG_SOC_AM43XX)		+= $(clk-common) dpll3xxx.o clk-43xx.o

					   clk-dra7-atl.o dpll3xxx.o \

					   dpll44xx.o clk-7xx-compat.o

obj-$(CONFIG_SOC_AM43XX)		+= $(clk-common) dpll3xxx.o clk-43xx.o \

					   clk-43xx-compat.o



endif	# CONFIG_ARCH_OMAP2PLUS

drivers/clk/ti/clk-33xx-compat.c

0 → 100644
+218 −0
Original line number Diff line number Diff line 
/*

 * AM33XX Clock init

 *

 * Copyright (C) 2013 Texas Instruments, Inc

 *     Tero Kristo (t-kristo@ti.com)

 *

 * This program is free software; you can redistribute it and/or

 * modify it under the terms of the GNU General Public License as

 * published by the Free Software Foundation version 2.

 *

 * This program is distributed "as is" WITHOUT ANY WARRANTY of any

 * kind, whether express or implied; without even the implied warranty

 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

 * GNU General Public License for more details.

 */



#include <linux/kernel.h>

#include <linux/list.h>

#include <linux/clk.h>

#include <linux/clk-provider.h>

#include <linux/clk/ti.h>

#include <dt-bindings/clock/am3.h>



#include "clock.h"



static const char * const am3_gpio1_dbclk_parents[] __initconst = {

	"l4_per_cm:clk:0138:0",

	NULL,

};



static const struct omap_clkctrl_bit_data am3_gpio2_bit_data[] __initconst = {

	{ 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },

	{ 0 },

};



static const struct omap_clkctrl_bit_data am3_gpio3_bit_data[] __initconst = {

	{ 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },

	{ 0 },

};



static const struct omap_clkctrl_bit_data am3_gpio4_bit_data[] __initconst = {

	{ 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },

	{ 0 },

};



static const struct omap_clkctrl_reg_data am3_l4_per_clkctrl_regs[] __initconst = {

	{ AM3_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk", "cpsw_125mhz_clkdm" },

	{ AM3_LCDC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "lcd_gclk", "lcdc_clkdm" },

	{ AM3_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "usbotg_fck", "l3s_clkdm" },

	{ AM3_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },

	{ AM3_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_div2_ck", "l3_clkdm" },

	{ AM3_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },

	{ AM3_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },

	{ AM3_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck", "l3s_clkdm" },

	{ AM3_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },

	{ AM3_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },

	{ AM3_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },

	{ AM3_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },

	{ AM3_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },

	{ AM3_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },

	{ AM3_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },

	{ AM3_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },

	{ AM3_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck", "l3s_clkdm" },

	{ AM3_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },

	{ AM3_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },

	{ AM3_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },

	{ AM3_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },

	{ AM3_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },

	{ AM3_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },

	{ AM3_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },

	{ AM3_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },

	{ AM3_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },

	{ AM3_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck", "l3_clkdm" },

	{ AM3_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },

	{ AM3_GPIO2_CLKCTRL, am3_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },

	{ AM3_GPIO3_CLKCTRL, am3_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },

	{ AM3_GPIO4_CLKCTRL, am3_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },

	{ AM3_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },

	{ AM3_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },

	{ AM3_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },

	{ AM3_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },

	{ AM3_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },

	{ AM3_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },

	{ AM3_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },

	{ AM3_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },

	{ AM3_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP, "pruss_ocp_gclk", "pruss_ocp_clkdm" },

	{ AM3_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },

	{ AM3_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },

	{ AM3_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },

	{ AM3_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk", "l3s_clkdm" },

	{ AM3_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },

	{ AM3_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },

	{ AM3_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },

	{ AM3_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },

	{ AM3_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk", "l4hs_clkdm" },

	{ AM3_OCPWP_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },

	{ AM3_CLKDIV32K_CLKCTRL, NULL, CLKF_SW_SUP, "clkdiv32k_ck", "clk_24mhz_clkdm" },

	{ 0 },

};



static const char * const am3_gpio0_dbclk_parents[] __initconst = {

	"gpio0_dbclk_mux_ck",

	NULL,

};



static const struct omap_clkctrl_bit_data am3_gpio1_bit_data[] __initconst = {

	{ 18, TI_CLK_GATE, am3_gpio0_dbclk_parents, NULL },

	{ 0 },

};



static const char * const am3_dbg_sysclk_ck_parents[] __initconst = {

	"sys_clkin_ck",

	NULL,

};



static const char * const am3_trace_pmd_clk_mux_ck_parents[] __initconst = {

	"l4_wkup_cm:clk:0010:19",

	"l4_wkup_cm:clk:0010:30",

	NULL,

};



static const char * const am3_trace_clk_div_ck_parents[] __initconst = {

	"l4_wkup_cm:clk:0010:20",

	NULL,

};



static const struct omap_clkctrl_div_data am3_trace_clk_div_ck_data __initconst = {

	.max_div = 64,

	.flags = CLK_DIVIDER_POWER_OF_TWO,

};



static const char * const am3_stm_clk_div_ck_parents[] __initconst = {

	"l4_wkup_cm:clk:0010:22",

	NULL,

};



static const struct omap_clkctrl_div_data am3_stm_clk_div_ck_data __initconst = {

	.max_div = 64,

	.flags = CLK_DIVIDER_POWER_OF_TWO,

};



static const char * const am3_dbg_clka_ck_parents[] __initconst = {

	"dpll_core_m4_ck",

	NULL,

};



static const struct omap_clkctrl_bit_data am3_debugss_bit_data[] __initconst = {

	{ 19, TI_CLK_GATE, am3_dbg_sysclk_ck_parents, NULL },

	{ 20, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL },

	{ 22, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL },

	{ 24, TI_CLK_DIVIDER, am3_trace_clk_div_ck_parents, &am3_trace_clk_div_ck_data },

	{ 27, TI_CLK_DIVIDER, am3_stm_clk_div_ck_parents, &am3_stm_clk_div_ck_data },

	{ 30, TI_CLK_GATE, am3_dbg_clka_ck_parents, NULL },

	{ 0 },

};



static const struct omap_clkctrl_reg_data am3_l4_wkup_clkctrl_regs[] __initconst = {

	{ AM3_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },

	{ AM3_GPIO1_CLKCTRL, am3_gpio1_bit_data, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },

	{ AM3_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },

	{ AM3_DEBUGSS_CLKCTRL, am3_debugss_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0010:24", "l3_aon_clkdm" },

	{ AM3_WKUP_M3_CLKCTRL, NULL, CLKF_NO_IDLEST, "dpll_core_m4_div2_ck", "l4_wkup_aon_clkdm" },

	{ AM3_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },

	{ AM3_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },

	{ AM3_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck" },

	{ AM3_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck" },

	{ AM3_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" },

	{ AM3_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck" },

	{ AM3_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck" },

	{ 0 },

};



static const struct omap_clkctrl_reg_data am3_mpu_clkctrl_regs[] __initconst = {

	{ AM3_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" },

	{ 0 },

};



static const struct omap_clkctrl_reg_data am3_l4_rtc_clkctrl_regs[] __initconst = {

	{ AM3_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk_32768_ck" },

	{ 0 },

};



static const struct omap_clkctrl_reg_data am3_gfx_l3_clkctrl_regs[] __initconst = {

	{ AM3_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" },

	{ 0 },

};



static const struct omap_clkctrl_reg_data am3_l4_cefuse_clkctrl_regs[] __initconst = {

	{ AM3_CEFUSE_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" },

	{ 0 },

};



const struct omap_clkctrl_data am3_clkctrl_compat_data[] __initconst = {

	{ 0x44e00014, am3_l4_per_clkctrl_regs },

	{ 0x44e00404, am3_l4_wkup_clkctrl_regs },

	{ 0x44e00604, am3_mpu_clkctrl_regs },

	{ 0x44e00800, am3_l4_rtc_clkctrl_regs },

	{ 0x44e00904, am3_gfx_l3_clkctrl_regs },

	{ 0x44e00a20, am3_l4_cefuse_clkctrl_regs },

	{ 0 },

};



struct ti_dt_clk am33xx_compat_clks[] = {

	DT_CLK(NULL, "timer_32k_ck", "l4_per_cm:0138:0"),

	DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),

	DT_CLK(NULL, "clkdiv32k_ick", "l4_per_cm:0138:0"),

	DT_CLK(NULL, "dbg_clka_ck", "l4_wkup_cm:0010:30"),

	DT_CLK(NULL, "dbg_sysclk_ck", "l4_wkup_cm:0010:19"),

	DT_CLK(NULL, "gpio0_dbclk", "l4_wkup_cm:0004:18"),

	DT_CLK(NULL, "gpio1_dbclk", "l4_per_cm:0098:18"),

	DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:009c:18"),

	DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:00a0:18"),

	DT_CLK(NULL, "stm_clk_div_ck", "l4_wkup_cm:0010:27"),

	DT_CLK(NULL, "stm_pmd_clock_mux_ck", "l4_wkup_cm:0010:22"),

	DT_CLK(NULL, "trace_clk_div_ck", "l4_wkup_cm:0010:24"),

	DT_CLK(NULL, "trace_pmd_clk_mux_ck", "l4_wkup_cm:0010:20"),

	{ .node_name = NULL },

};

drivers/clk/ti/clk-33xx.c

+140 −92

File changed.

Preview size limit exceeded, changes collapsed.

drivers/clk/ti/clk-43xx-compat.c

0 → 100644
+225 −0
Original line number Diff line number Diff line 
/*

 * AM43XX Clock init

 *

 * Copyright (C) 2013 Texas Instruments, Inc

 *     Tero Kristo (t-kristo@ti.com)

 *

 * This program is free software; you can redistribute it and/or

 * modify it under the terms of the GNU General Public License as

 * published by the Free Software Foundation version 2.

 *

 * This program is distributed "as is" WITHOUT ANY WARRANTY of any

 * kind, whether express or implied; without even the implied warranty

 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

 * GNU General Public License for more details.

 */



#include <linux/kernel.h>

#include <linux/list.h>

#include <linux/clk.h>

#include <linux/clk-provider.h>

#include <linux/clk/ti.h>

#include <dt-bindings/clock/am4.h>



#include "clock.h"



static const char * const am4_synctimer_32kclk_parents[] __initconst = {

	"mux_synctimer32k_ck",

	NULL,

};



static const struct omap_clkctrl_bit_data am4_counter_32k_bit_data[] __initconst = {

	{ 8, TI_CLK_GATE, am4_synctimer_32kclk_parents, NULL },

	{ 0 },

};



static const char * const am4_gpio0_dbclk_parents[] __initconst = {

	"gpio0_dbclk_mux_ck",

	NULL,

};



static const struct omap_clkctrl_bit_data am4_gpio1_bit_data[] __initconst = {

	{ 8, TI_CLK_GATE, am4_gpio0_dbclk_parents, NULL },

	{ 0 },

};



static const struct omap_clkctrl_reg_data am4_l4_wkup_clkctrl_regs[] __initconst = {

	{ AM4_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck", "l3s_tsc_clkdm" },

	{ AM4_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" },

	{ AM4_WKUP_M3_CLKCTRL, NULL, CLKF_NO_IDLEST, "sys_clkin_ck" },

	{ AM4_COUNTER_32K_CLKCTRL, am4_counter_32k_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0210:8" },

	{ AM4_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck", "l4_wkup_clkdm" },

	{ AM4_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck", "l4_wkup_clkdm" },

	{ AM4_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck", "l4_wkup_clkdm" },

	{ AM4_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck", "l4_wkup_clkdm" },

	{ AM4_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck", "l4_wkup_clkdm" },

	{ AM4_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck", "l4_wkup_clkdm" },

	{ AM4_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" },

	{ AM4_GPIO1_CLKCTRL, am4_gpio1_bit_data, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" },

	{ 0 },

};



static const struct omap_clkctrl_reg_data am4_mpu_clkctrl_regs[] __initconst = {

	{ AM4_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" },

	{ 0 },

};



static const struct omap_clkctrl_reg_data am4_gfx_l3_clkctrl_regs[] __initconst = {

	{ AM4_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" },

	{ 0 },

};



static const struct omap_clkctrl_reg_data am4_l4_rtc_clkctrl_regs[] __initconst = {

	{ AM4_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk_32768_ck" },

	{ 0 },

};



static const char * const am4_usb_otg_ss0_refclk960m_parents[] __initconst = {

	"dpll_per_clkdcoldo",

	NULL,

};



static const struct omap_clkctrl_bit_data am4_usb_otg_ss0_bit_data[] __initconst = {

	{ 8, TI_CLK_GATE, am4_usb_otg_ss0_refclk960m_parents, NULL },

	{ 0 },

};



static const struct omap_clkctrl_bit_data am4_usb_otg_ss1_bit_data[] __initconst = {

	{ 8, TI_CLK_GATE, am4_usb_otg_ss0_refclk960m_parents, NULL },

	{ 0 },

};



static const char * const am4_gpio1_dbclk_parents[] __initconst = {

	"clkdiv32k_ick",

	NULL,

};



static const struct omap_clkctrl_bit_data am4_gpio2_bit_data[] __initconst = {

	{ 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },

	{ 0 },

};



static const struct omap_clkctrl_bit_data am4_gpio3_bit_data[] __initconst = {

	{ 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },

	{ 0 },

};



static const struct omap_clkctrl_bit_data am4_gpio4_bit_data[] __initconst = {

	{ 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },

	{ 0 },

};



static const struct omap_clkctrl_bit_data am4_gpio5_bit_data[] __initconst = {

	{ 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },

	{ 0 },

};



static const struct omap_clkctrl_bit_data am4_gpio6_bit_data[] __initconst = {

	{ 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },

	{ 0 },

};



static const struct omap_clkctrl_reg_data am4_l4_per_clkctrl_regs[] __initconst = {

	{ AM4_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },

	{ AM4_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck", "l3_clkdm" },

	{ AM4_DES_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },

	{ AM4_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },

	{ AM4_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },

	{ AM4_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },

	{ AM4_VPFE0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3s_clkdm" },

	{ AM4_VPFE1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3s_clkdm" },

	{ AM4_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },

	{ AM4_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },

	{ AM4_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },

	{ AM4_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },

	{ AM4_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk", "l3_clkdm" },

	{ AM4_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },

	{ AM4_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck", "l3s_clkdm" },

	{ AM4_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck", "l3s_clkdm" },

	{ AM4_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk", "l3s_clkdm" },

	{ AM4_QSPI_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },

	{ AM4_USB_OTG_SS0_CLKCTRL, am4_usb_otg_ss0_bit_data, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },

	{ AM4_USB_OTG_SS1_CLKCTRL, am4_usb_otg_ss1_bit_data, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },

	{ AM4_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP, "pruss_ocp_gclk", "pruss_ocp_clkdm" },

	{ AM4_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },

	{ AM4_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },

	{ AM4_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },

	{ AM4_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },

	{ AM4_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },

	{ AM4_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },

	{ AM4_EPWMSS3_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },

	{ AM4_EPWMSS4_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },

	{ AM4_EPWMSS5_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },

	{ AM4_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },

	{ AM4_GPIO2_CLKCTRL, am4_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },

	{ AM4_GPIO3_CLKCTRL, am4_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },

	{ AM4_GPIO4_CLKCTRL, am4_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },

	{ AM4_GPIO5_CLKCTRL, am4_gpio5_bit_data, CLKF_SW_SUP, "l4ls_gclk" },

	{ AM4_GPIO6_CLKCTRL, am4_gpio6_bit_data, CLKF_SW_SUP, "l4ls_gclk" },

	{ AM4_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_clk" },

	{ AM4_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },

	{ AM4_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },

	{ AM4_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },

	{ AM4_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },

	{ AM4_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },

	{ AM4_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },

	{ AM4_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },

	{ AM4_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },

	{ AM4_SPI2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },

	{ AM4_SPI3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },

	{ AM4_SPI4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },

	{ AM4_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },

	{ AM4_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },

	{ AM4_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },

	{ AM4_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },

	{ AM4_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },

	{ AM4_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },

	{ AM4_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },

	{ AM4_TIMER8_CLKCTRL, NULL, CLKF_SW_SUP, "timer8_fck" },

	{ AM4_TIMER9_CLKCTRL, NULL, CLKF_SW_SUP, "timer9_fck" },

	{ AM4_TIMER10_CLKCTRL, NULL, CLKF_SW_SUP, "timer10_fck" },

	{ AM4_TIMER11_CLKCTRL, NULL, CLKF_SW_SUP, "timer11_fck" },

	{ AM4_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },

	{ AM4_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },

	{ AM4_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },

	{ AM4_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },

	{ AM4_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },

	{ AM4_OCP2SCP0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },

	{ AM4_OCP2SCP1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },

	{ AM4_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_ck", "emif_clkdm" },

	{ AM4_DSS_CORE_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "disp_clk", "dss_clkdm" },

	{ AM4_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk", "cpsw_125mhz_clkdm" },

	{ 0 },

};



const struct omap_clkctrl_data am4_clkctrl_compat_data[] __initconst = {

	{ 0x44df2820, am4_l4_wkup_clkctrl_regs },

	{ 0x44df8320, am4_mpu_clkctrl_regs },

	{ 0x44df8420, am4_gfx_l3_clkctrl_regs },

	{ 0x44df8520, am4_l4_rtc_clkctrl_regs },

	{ 0x44df8820, am4_l4_per_clkctrl_regs },

	{ 0 },

};



const struct omap_clkctrl_data am438x_clkctrl_compat_data[] __initconst = {

	{ 0x44df2820, am4_l4_wkup_clkctrl_regs },

	{ 0x44df8320, am4_mpu_clkctrl_regs },

	{ 0x44df8420, am4_gfx_l3_clkctrl_regs },

	{ 0x44df8820, am4_l4_per_clkctrl_regs },

	{ 0 },

};



struct ti_dt_clk am43xx_compat_clks[] = {

	DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"),

	DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),

	DT_CLK(NULL, "gpio0_dbclk", "l4_wkup_cm:0348:8"),

	DT_CLK(NULL, "gpio1_dbclk", "l4_per_cm:0458:8"),

	DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:0460:8"),

	DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:0468:8"),

	DT_CLK(NULL, "gpio4_dbclk", "l4_per_cm:0470:8"),

	DT_CLK(NULL, "gpio5_dbclk", "l4_per_cm:0478:8"),

	DT_CLK(NULL, "synctimer_32kclk", "l4_wkup_cm:0210:8"),

	DT_CLK(NULL, "usb_otg_ss0_refclk960m", "l4_per_cm:0240:8"),

	DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l4_per_cm:0248:8"),

	{ .node_name = NULL },

};