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Commit 3d15a4dd authored by Prakash Gupta's avatar Prakash Gupta
Browse files

iommu: arm-smmu: update SID info print 



Print SSD info in the context fault handler. This is useful to
differentiate transaction generated within SMMU to those from actual
clients.

While we are at it, also move SID print before we start ATOS operations.
Sometime it's observed that if system triggers panic before fault handler
completes ATOS operations then the SID info is not printed. SID info has
been found to be must in order to identify the master. So print it before
we start ATOS operation.

Change-Id: I1391686510ef8d61bf11b83102c884b5fa433abd
Signed-off-by: default avatarPrakash Gupta <guptap@codeaurora.org>
parent 12007b0e

drivers/iommu/arm-smmu-qcom.c

+1 −2
Original line number Diff line number Diff line
@@ -1633,8 +1633,7 @@ static phys_addr_t qsmmuv500_iova_to_phys_hard( 
		 */

		frsynra = arm_smmu_gr1_read(smmu,

					    ARM_SMMU_GR1_CBFRSYNRA(cfg->cbndx));

		frsynra &= CBFRSYNRA_SID_MASK;

		sid      = frsynra;

		sid = FIELD_GET(CBFRSYNRA_SID, frsynra);

	}

	return qsmmuv500_iova_to_phys(smmu_domain, iova, sid, trans_flags);

}

drivers/iommu/arm-smmu.c

+5 −2
Original line number Diff line number Diff line
@@ -1373,7 +1373,6 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev) 
	iova = arm_smmu_cb_readq(smmu, idx, ARM_SMMU_CB_FAR);

	phys_soft = arm_smmu_iova_to_phys(domain, iova);

	frsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(cfg->cbndx));

	frsynra &= CBFRSYNRA_SID_MASK;

	tmp = report_iommu_fault(domain, smmu->dev, iova, flags);

	if (!tmp || (tmp == -EBUSY)) {

		dev_dbg(smmu->dev,
@@ -1398,6 +1397,11 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev) 
			dev_err(smmu->dev,

				"Unhandled context fault: iova=0x%08lx, cb=%d, fsr=0x%x, fsynr0=0x%x, fsynr1=0x%x\n",

				iova, cfg->cbndx, fsr, fsynr0, fsynr1);



			dev_err(smmu->dev, "SSD=0x%x SID=0x%x\n",

				FIELD_GET(CBFRSYNRA_SSD, frsynra),

				FIELD_GET(CBFRSYNRA_SID, frsynra));



			dev_err(smmu->dev,

				"Client info: BID=0x%lx, PID=0x%lx, MID=0x%lx\n",

				FIELD_GET(FSYNR1_BID, fsynr1),
@@ -1419,7 +1423,6 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev) 
					&phys_atos);

			else

				dev_err(smmu->dev, "hard iova-to-phys (ATOS) failed\n");

			dev_err(smmu->dev, "SID=0x%x\n", frsynra);

		}

		ret = IRQ_HANDLED;

		resume = RESUME_TERMINATE;

drivers/iommu/arm-smmu.h

+3 −1
Original line number Diff line number Diff line
@@ -139,7 +139,9 @@ enum arm_smmu_cbar_type { 
#define CBAR_VMID			GENMASK(7, 0)



#define ARM_SMMU_GR1_CBFRSYNRA(n)	(0x400 + ((n) << 2))

#define CBFRSYNRA_SID_MASK		(0xffff)

#define CBFRSYNRA_SID			GENMASK(15, 0)

#define CBFRSYNRA_SSD			GENMASK(31, 16)





#define ARM_SMMU_GR1_CBA2R(n)		(0x800 + ((n) << 2))

#define CBA2R_VMID16			GENMASK(31, 16)