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Commit 3d099a05 authored by Daniel Vetter's avatar Daniel Vetter
Browse files

drm/i915: Add new CRC sources 



On pre-gen5 and vlv we can't use the pipe source when TV-out or a DP
port is connected to the pipe. Hence we need to expose new CRC
sources.

Also simplify the existing pipe source platform code a bit by
rejecting all unhandled sources by default.

Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent b073aeaa

drivers/gpu/drm/i915/i915_debugfs.c

+10 −6
Original line number Diff line number Diff line
@@ -1915,6 +1915,10 @@ static const char * const pipe_crc_sources[] = { 
	"plane2",

	"pf",

	"pipe",

	"TV",

	"DP-B",

	"DP-C",

	"DP-D",

};



static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
@@ -1953,14 +1957,14 @@ static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source source, 
	case INTEL_PIPE_CRC_SOURCE_PLANE2:

		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;

		break;

	case INTEL_PIPE_CRC_SOURCE_PF:

		return -EINVAL;

	case INTEL_PIPE_CRC_SOURCE_PIPE:

		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;

		break;

	default:

	case INTEL_PIPE_CRC_SOURCE_NONE:

		*val = 0;

		break;

	default:

		return -EINVAL;

	}



	return 0;
@@ -1979,11 +1983,11 @@ static int ivb_pipe_crc_ctl_reg(enum intel_pipe_crc_source source, 
	case INTEL_PIPE_CRC_SOURCE_PF:

		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;

		break;

	case INTEL_PIPE_CRC_SOURCE_PIPE:

		return -EINVAL;

	default:

	case INTEL_PIPE_CRC_SOURCE_NONE:

		*val = 0;

		break;

	default:

		return -EINVAL;

	}



	return 0;

drivers/gpu/drm/i915/i915_drv.h

+5 −0
Original line number Diff line number Diff line
@@ -1224,6 +1224,11 @@ enum intel_pipe_crc_source { 
	INTEL_PIPE_CRC_SOURCE_PLANE2,

	INTEL_PIPE_CRC_SOURCE_PF,

	INTEL_PIPE_CRC_SOURCE_PIPE,

	/* TV/DP on pre-gen5/vlv can't use the pipe source. */

	INTEL_PIPE_CRC_SOURCE_TV,

	INTEL_PIPE_CRC_SOURCE_DP_B,

	INTEL_PIPE_CRC_SOURCE_DP_C,

	INTEL_PIPE_CRC_SOURCE_DP_D,

	INTEL_PIPE_CRC_SOURCE_MAX,

};