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Commit 3cf10132 authored by Sébastien Szymanski's avatar Sébastien Szymanski Committed by Shawn Guo
Browse files

ARM: dts: imx6ul: fix PWM[1-4] interrupts 



According to the i.MX6UL/L RM, table 3.1 "ARM Cortex A7 domain interrupt
summary", the interrupts for the PWM[1-4] go from 83 to 86.

Fixes: b9901fe8 ("ARM: dts: imx6ul: add pwm[1-4] nodes")
Signed-off-by: default avatarSébastien Szymanski <sebastien.szymanski@armadeus.com>
Reviewed-by: default avatarFabio Estevam <festevam@gmail.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent a019ab40

arch/arm/boot/dts/imx6ul.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -358,7 +358,7 @@ 
			pwm1: pwm@2080000 {

				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";

				reg = <0x02080000 0x4000>;

				interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;

				interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clks IMX6UL_CLK_PWM1>,

					 <&clks IMX6UL_CLK_PWM1>;

				clock-names = "ipg", "per";
@@ -369,7 +369,7 @@ 
			pwm2: pwm@2084000 {

				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";

				reg = <0x02084000 0x4000>;

				interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;

				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clks IMX6UL_CLK_PWM2>,

					 <&clks IMX6UL_CLK_PWM2>;

				clock-names = "ipg", "per";
@@ -380,7 +380,7 @@ 
			pwm3: pwm@2088000 {

				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";

				reg = <0x02088000 0x4000>;

				interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;

				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clks IMX6UL_CLK_PWM3>,

					 <&clks IMX6UL_CLK_PWM3>;

				clock-names = "ipg", "per";
@@ -391,7 +391,7 @@ 
			pwm4: pwm@208c000 {

				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";

				reg = <0x0208c000 0x4000>;

				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;

				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clks IMX6UL_CLK_PWM4>,

					 <&clks IMX6UL_CLK_PWM4>;

				clock-names = "ipg", "per";