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Commit 3cd049ab authored by Bharat Kumar Gogada's avatar Bharat Kumar Gogada Committed by Bjorn Helgaas
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PCI: xilinx: Clear interrupt register for invalid interrupt 



The interrupt decode register is not being cleared if an invalid interrupt
arises.  Clear the decode register in this case.

Signed-off-by: default avatarBharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Acked-by: default avatarMichal Simek <michal.simek@xilinx.com>
parent b584fa1f

drivers/pci/host/pcie-xilinx.c

+3 −2
Original line number Original line Diff line number Diff line
@@ -434,7 +434,7 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data) 
		/* Check whether interrupt valid */

		/* Check whether interrupt valid */

		if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) {

		if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) {

			dev_warn(port->dev, "RP Intr FIFO1 read error\n");

			dev_warn(port->dev, "RP Intr FIFO1 read error\n");

			return IRQ_HANDLED;

			goto error;

		}

		}





		if (!(val & XILINX_PCIE_RPIFR1_MSI_INTR)) {

		if (!(val & XILINX_PCIE_RPIFR1_MSI_INTR)) {
@@ -456,7 +456,7 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data) 




		if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) {

		if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) {

			dev_warn(port->dev, "RP Intr FIFO1 read error\n");

			dev_warn(port->dev, "RP Intr FIFO1 read error\n");

			return IRQ_HANDLED;

			goto error;

		}

		}





		if (val & XILINX_PCIE_RPIFR1_MSI_INTR) {

		if (val & XILINX_PCIE_RPIFR1_MSI_INTR) {
@@ -501,6 +501,7 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data) 
	if (status & XILINX_PCIE_INTR_MST_ERRP)

	if (status & XILINX_PCIE_INTR_MST_ERRP)

		dev_warn(port->dev, "Master error poison\n");

		dev_warn(port->dev, "Master error poison\n");





error:

	/* Clear the Interrupt Decode register */

	/* Clear the Interrupt Decode register */

	pcie_write(port, status, XILINX_PCIE_REG_IDR);

	pcie_write(port, status, XILINX_PCIE_REG_IDR);